Abstract: A technique for controlling memory accesses of a data stream is provided. The data is streamed between selected ports of a plurality of ports coupled to a memory (110). As to a method aspect of the technique, a pool of ports is selected. The selected ports include a first port (112) and a second port (118) through which data is to be streamed. A portion of the memory (110) is allocated to the pool of ports. The first port (112) is configured for write access to the allocated memory. The second port (118) is configured for read access to the allocated memory. In dependence on a first state indicative of the occurrence of a write access using the first port (112) and a second state indicative of the occurrence of a read access using the second port (118), a further write access using the first port (112) and/or a further read access using the second part (118) is controlled.

Abstract: A technique for controlling memory accesses of a data stream is provided. The data is streamed between selected ports of a plurality of ports coupled to a memory (110). As to a method aspect of the technique, a pool of ports is selected. The selected ports include a first port (112) and a second port (118) through which data is to be streamed. A portion of the memory (110) is allocated to the pool of ports. The first port (112) is configured for write access to the allocated memory. The second port (118) is configured for read access to the allocated memory. In dependence on a first state indicative of the occurrence of a write access using the first port (112) and a second state indicative of the occurrence of a read access using the second port (118), a further write access using the first port (112) and/or a further read access using the second part (118) is controlled.