Abstract: Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is varied so as to provide a predetermined processed clock signal duty cycle. The predetermined duty cycle is preferably a 50—50 duty cycle. The output node may be coupled to baseband circuitry of a wireless communications terminal, such as a cellular telephone. The circuit is constructed to include a plurality of serially connected delay elements that are coupled to the clock signal at the input node. The plurality of delay elements together introduce a nominal one cycle delay into the clock signal.

Abstract: Disclosed is a circuit for controlling the duty cycle and jitter of a clock signal. The circuit has an input node for receiving the clock signal and an output node for outputting a processed clock signal having a first edge that is synchronized to an edge of the clock signal and a second edge that is varied so as to provide a predetermined processed clock signal duty cycle. The predetermined duty cycle is preferably a 50-50 duty cycle. The output node may be coupled to baseband circuitry of a wireless communications terminal, such as a cellular telephone. The circuit is constructed to include a plurality of serially connected delay elements that are coupled to the clock signal at the input node. The plurality of delay elements together introduce a nominal one cycle delay into the clock signal.