Patents by Inventor Juha Nurminen

Juha Nurminen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070046519
    Abstract: A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.
    Type: Application
    Filed: October 27, 2006
    Publication date: March 1, 2007
    Inventors: Juha Hakkarainen, Juha Nurminen
  • Publication number: 20050017321
    Abstract: A capacitor array in an integrated circuit with active unit capacitor cells arranged amongst the dummy unit capacitor cells to provide visual and electrical symmetry. The electrical symmetry provides electrical matching between active unit capacitor cells and the visual symmetry provide process uniformity between the unit capacitor cells. Visual symmetry may be provided by uniform capacitor plate selection and uniform spacing between each. Electrical symmetry is provided by appropriately arranging active unit capacitors amongst dummy unit capacitors in the capacitor array. The capacitor array may be used in an integrated circuit such as for a equally weighted or binary weighted capacitor array or ladder in an analog to digital converter or a digital to analog converter. Methods and rules of layout for arranging the unit capacitors may be manually performed or automatically performed by computer aided design software.
    Type: Application
    Filed: July 22, 2003
    Publication date: January 27, 2005
    Inventors: Juha Hakkarainen, Juha Nurminen
  • Patent number: 6794930
    Abstract: The invention relates to a method for improving the quality of the output signal of especially an audio output stage, which comprises at least a modulator circuit, in such a manner that in accordance with the method a signal generated in the output stage, which signal is proportional to a previous digital input signal, is compared by means of feedback to the digital input signal (IN) of the output stage in order to generate a digital control signal (307), and the operation of said modulator circuit (301) is controlled by means of said digital control signal (307).
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: September 21, 2004
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Juha Nurminen