Abstract: A method and a circuit arrangement for implementing timing between a microprocessor and its peripheral devices. An address bus and a data bus connect the microprocessor to the peripheral devices to transfer data from the microprocessor to a selected peripheral device, corresponding to writing to the peripheral device, and from a selected peripheral device to the microprocessor, corresponding to reading from the peripheral device. The method comprises generating to the peripheral devices (a) a signal controlling reading (Output Enable), which enables a peripheral device to apply data to the data bus, and (b) a signal controlling writing (Write Enable), which enables data to be written from the data bus to a peripheral device.