Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchronizer, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchroniser, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain.

Abstract: An architecture is shown where a conventional direct memory access structure is replaced with a latency tolerant programmable direct memory access engine, or co-processor, that can handle multiple demanding data streaming operations in parallel. The co-processor concept includes a latency tolerant programmable core with any number of tightly coupled auxiliary units. The co-processor operates in parallel with any number of host processors, thereby reducing the host processors' load as the co-processor is configured to autonomously execute assigned tasks.

Abstract: A method and apparatus are provided to arbitrate multiple master requests to a shared resource, featuring a step of combining two different ways to arbitrate the multiple master requests to the shared resource in an operation independent manner. The two different ways may include a priority arbitration technique and a round robin arbitration technique. The priority arbitration technique may include a time division priority selection technique. The shared resource may include a set of one or more peripherals and/or memories. The step may be implemented in an application specific integrated circuit (ASIC) or other suitable application environment, which includes video, graphic, cellular or other suitable functionality.

Abstract: The invention relates to a method in a hardware semaphore lock (L1–LN) intended for a multi-processor system, which semaphore lock (L1–LN) protects a shared resource (R1–RN) in connection with the system in such a way that only a process which has reserved the semaphore lock (L1–LN) and has thus become a holder of the lock, has access to use the resource protected by the lock. The semaphore lock (L1–LN) is reserved by a single read operation of a memory location representing the semaphore lock by the process software. The read operation returns to the process the number of vacant holder positions, i.e. keyholes vacant at the time of the reservation of the lock. The semaphore lock does not require the support of the system for atomic read/write operations.

Abstract: The invention relates to a method in a hardware semaphore lock (L1–LN) intended for a multi-processor system, which semaphore lock (L1–LN) protects a shared resource (R1–RN) in connection with the system in such a way that only a process which has reserved the semaphore lock (L1–LN) and has thus become a holder of the lock, has access to use the resource protected by the lock. The semaphore lock (L1–LN) is reserved by a single read operation of a memory location representing the semaphore lock by the process software. The read operation returns to the process the number of vacant holder positions, i.e. keyholes vacant at the time of the reservation of the lock. The semaphore lock does not require the support of the system for atomic read/write operations.

Abstract: A method and device is disclosed for implementing dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one or several hardware units (201, 202, 203), a hardware based power control logic (204) substantially implemented with logic circuits, as well as a programmable power control mode register (208) containing information about powered-down modes defined for said one or more hardware units. To transfer a single hardware unit (201, 202, 203) from the powered-down mode to the operational mode, the hardware unit transmits to the power control logic (204) a first level sensitive status signal (201a, 202a, 203a) for transferring the hardware unit from the powered-down mode to the wake up mode, and further a second level sensitive status signal (201b, 202b, 203b) for transferring the hardware unit from the wake up mode to the actual operating mode.

Abstract: An arrangement for collecting operational information on a closed system. The collecting system comprises an instrument to be connected functionally to a monitorable component of the closed system and a data collector comprising a register. The instrument collects operational information on the component that is transmitted onward to the data collector. The operational information is stored in the register. The collecting system can also comprise an analyzing module that determines the performance and/or power consumption of the closed system on the basis of the received operational information. The collecting system can also comprise a controlling module comprising a control algorithm and being functionally connected to the analyzing module for adjusting the performance or power consumption of the closed system on the basis of analysis information.

Abstract: The invention relates to a method in a hardware semaphore lock (L1-LN) intended for a multi-processor system, which semaphore lock (L1-LN) protects a shared resource (R1-RN) in connection with said system in such a way that only a process which has reserved the semaphore lock (L1-LN) and has thus become a holder of said lock, has access to use the resource protected by said lock. According to the invention, the semaphore lock (L1-LN) is reserved by a single read operation of a memory location representing the semaphore lock by the process software. The read operation returns to the process the number of vacant holder positions, i.e. keyholes vacant at the time of the reservation of said lock. The most significant advantage of the invention is that the implementation of the semaphore lock does not require the support of the system for atomic read/write operations.

Abstract: A method and device is disclosed for implementing dynamic power control in an electronic system implemented on an integrated circuit, which electronic system comprises at least one or several hardware units (201, 202, 203), a hardware based power control logic (204) substantially implemented with logic circuits, as well as a programmable power control mode register (208) containing information about powered-down modes defined for said one or more hardware units. To transfer a single hardware unit (201, 202, 203) from the powered-down mode to the operational mode, the hardware unit transmits to the power control logic (204) a first level sensitive status signal (201a, 202a, 203a) for transferring the hardware unit from the powered-down mode to the wake up mode, and further a second level sensitive status signal (201b, 202b, 203b) for transferring the hardware unit from the wake up mode to the actual operating mode.

Abstract: The invention relates to a method for enabling in a processing system a communication between at least two activated processes 22,23. In order to improve the communication between different processes 22,23 of a processing system, it is proposed that for said communication signals are transmitted between said at least two processes 22,23 in virtual channels using the same physical channel 28. This enables an efficient use of physical resources. A corresponding processing system comprises at least one processor 50-52 for running different processes, at least one physical channel provided for enabling a communication between at least two of said different processes, and means 55-57 for distributing signals which are to be transmitted for such a communication between said at least two different processes to different virtual channels on said at least one physical channel.

Abstract: A data processing circuit is arranged to execute program instructions defining nested loops. A loop is defined in terms of a start address, an end address and a number of loop iterations. The processing circuit includes a program counter and a plurality of loop counting elements. Each of the loop counting elements includes a start address register, an end address register, a loop iteration register and means for comparing the value stored in the respective end address register with the output from the program counter.