Abstract: A display device in one example includes a display panel configured to display an image and a gate signal generating circuit configured to supply a gate signal to the display panel. The gate signal generating circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on a voltage of the Q node to output the gate signal. The signal output circuit includes at least one pull-up transistor and at least one pull-down transistor each including a gate electrode connected to the Q node in common.

Abstract: A display device in one example includes a display panel configured to display an image and a gate signal generating circuit configured to supply a gate signal to the display panel. The gate signal generating circuit includes a signal control circuit configured to control a Q node and a signal output circuit configured to operate based on a voltage of the Q node to output the gate signal. The signal output circuit includes at least one pull-up transistor and at least one pull-down transistor each including a gate electrode connected to the Q node in common.

Abstract: An organic light emitting display device, in which a silicon semiconductor pattern is formed on a buffer layer, and light shielding patterns of a pixel driving thin film transistor and a switching thin film transistor are then formed in the same process by processing portions of the silicon semiconductor pattern such that the portions of the silicon semiconductor pattern have conductivity, is disclosed. In a procedure of forming the silicon semiconductor pattern for formation of the light shielding patterns, a silicon semiconductor pattern, which is disposed under a gate driving thin film transistor, may be formed simultaneously with the former silicon semiconductor pattern, without using an additional silicon semiconductor pattern formation procedure. Accordingly, stack structures, planar design, and processes are simplified and, as such, there are effects of preventing failure occurring due to processes while reducing tact time and costs.

Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.

Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.