Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

Abstract: An integrated circuit device includes: a substrate including a device area and a field area; active regions extending in a first direction in the device area; a first gate structure extending in a second direction intersecting the first direction in the device area and the field area; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact disposed on the first gate structure in the device area; and a second gate contact disposed on the second gate structure in the field area, wherein the first gate contact and the second gate contact are disposed at a level lower than an upper end of the first gate structure, and wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other.

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

Abstract: A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

Abstract: A semiconductor device includes first to fourth gate structures sequentially disposed in a first horizontal direction. Each of the first to fourth gate structures includes a gate electrode and a gate capping layer and first to third source/drain regions disposed among the first to fourth gate structures. A first narrow source/drain contact, a first wide source/drain contact, and a second narrow source/drain contact are disposed among the first to fourth gate structures and contact the first to third source/drain regions, respectively. The first to fourth gate structures are disposed with first to third distances there among. The second distance is greater than the first distance and the third distance. A lower end of the first narrow source/drain contact is disposed at a higher level than a lower end of the first wide source/drain contact.

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

Abstract: An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

Abstract: Integrated circuit devices may include a fin-type active region, a gate line extending on the fin-type active region, a source/drain region on the fin-type active region and adjacent to the gate line, an interlayer insulating film covering the source/drain region, a source/drain contact hole penetrating the interlayer insulating film toward the source/drain region, a metal plug in the source/drain contact hole, and a conductive barrier film covering a sidewall of the metal plug in the source/drain contact hole. The metal plug includes a lateral expansion portion and a through portion vertically extending from the lateral expansion portion toward the source/drain region. A width of the lateral expansion is greater than a width of the through portion, and a topmost surface of the conductive barrier film is closer than a topmost surface of the metal plug to the substrate.

Abstract: A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.

Abstract: A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

Abstract: A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

Abstract: Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.