Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Abstract: A storage controller and an operating method of the storage controller are provided. The storage controller includes processing circuitry configured to read sub-stripe data from each of a plurality of non-volatile memory devices connected with a RAID (Redundant Array of Inexpensive Disk), check error information of at least one of the sub-stripe data, and perform a RAID recovery operation in response to the at least one of the sub-stripe data having an uncorrectable error, and a RAID memory which stores calculation results of the RAID recovery operation.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: An error checking and correcting (ECC) circuit is connected with nonvolatile memories via a plurality of channels. The ECC circuit calculates a first syndrome according to first read data and stores the first syndrome in a first syndrome register block, and calculates a second syndrome according to second read data and stores the second syndrome in a second syndrome register block.

Abstract: A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Abstract: A digital signal processor, a receiver, a corrector, and methods for the same are provided. An analog circuit may output sample data based on received input data. A digital circuit may generate a baseline wander error based on the sample data and output data output from the digital circuit. A baseline wander error correction value may be generated based on the generated baseline wander error.