Patents by Inventor Jui-Chang TSAO

Jui-Chang TSAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10931787
    Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chen-Kuo Hwang, Jui-Chang Tsao
  • Patent number: 10693478
    Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 23, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chang Tsao, Chen-Kuo Hwang, Po-Wei Liu
  • Publication number: 20200076921
    Abstract: A method of forwarding information base synchronization for a network switch stacking system includes transmitting by at least one slave network switch at least one change event to a master network switch, generating by the master network switch a change confirmation to the at least one slave network switch when a master forwarding information base is determined to be necessarily updated by the master network switch according to the at least one change event, and updating by the at least one slave network switch at least one slave forwarding information base according to the change confirmation, wherein the at least one change event includes at least one of a new learn event, a port move event, a regular port aging out event, a logic aggregation update aging time event.
    Type: Application
    Filed: March 26, 2019
    Publication date: March 5, 2020
    Inventors: Chen-Kuo Hwang, Jui-Chang Tsao
  • Publication number: 20200052707
    Abstract: A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 13, 2020
    Inventors: Jui-Chang TSAO, Chen-Kuo Hwang, Po-Wei LIU