Abstract: A power management system includes a first power line, a second power line, a first parallel protector, a second parallel protector, a third parallel protector, a first current sensor, a second current sensor, a third current sensor, and a processor. The first parallel protector is coupled to the first power line. The second parallel protector is coupled to the first parallel protector and the second power line. The third parallel protector is coupled to the first parallel protector and a ground terminal. The first current sensor, the second current sensor and the third current sensor respectively sense a first current flowing through the first parallel protector, a second current flowing through the second parallel protector, and a third current flowing through the third parallel protector. The processor detects a surge discharging path according to the first current, the second current and/or the third current.

Abstract: A power management system includes a first power line, a second power line, a first parallel protector, a second parallel protector, a third parallel protector, a first current sensor, a second current sensor, a third current sensor, and a processor. The first parallel protector is coupled to the first power line. The second parallel protector is coupled to the first parallel protector and the second power line. The third parallel protector is coupled to the first parallel protector and a ground terminal. The first current sensor, the second current sensor and the third current sensor respectively sense a first current flowing through the first parallel protector, a second current flowing through the second parallel protector, and a third current flowing through the third parallel protector. The processor detects a surge discharging path according to the first current, the second current and/or the third current.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes an active inductor unit, a source injection unit, a first transistor and a second transistor. The injection-locked frequency divider generates a frequency-divided signal having a half frequency of the signal source. A locking frequency range of the injection-locked frequency divider is determined by a quality factor of a resonant cavity. A quality factor of the active inductor unit is lower than a conventional spiral inductor because the active inductor unit is composed of active elements. In the injection-locked frequency divider, the active inductor unit is used to instead of the conventional spiral inductor, so that the chip area can be reduced and the locking frequency range of the injection-locked frequency divider can be increased. Further, an induction value of the active inductor unit can be altered to change the locking frequency range of the injection-locked frequency divider.

Abstract: An injection-locked frequency divider is provided. The present invention includes an active inductor unit, a source injection unit, a first transistor and a second transistor. A first terminal of the active inductor unit is coupled to a first voltage. A first terminal of the source injection unit receives a signal source. A second terminal and a third terminal of the source injection unit are respectively coupled to a second terminal and a third terminal of the active inductor unit. A first terminal, a gate terminal and a second terminal of the first transistor are respectively coupled to the second terminal and the third terminal of the source injection unit and a second voltage. A first terminal, a gate terminal and a second terminal of the second transistor are respectively coupled to the third terminal and a second terminal of the source injection unit and the second voltage.