Patents by Inventor Jui-Cheng Huang

Jui-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11360045
    Abstract: In an embodiment, a device includes: an electrode configured to change a contact angle of a liquid droplet above the electrode when a first voltage is applied to the electrode; a sensing film overlaying the electrode, wherein the electrode is configured for assessment of a state of the liquid droplet based on a second voltage sensed at the electrode; a reference electrode above the electrode, the reference electrode configured to provide a reference voltage; and a microfluidic channel between the electrode and the reference electrode, wherein the microfluidic channel is configured to manipulate the liquid droplet using the electrode.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Tsun Chen, Allen Timothy Chang, Jui-Cheng Huang
  • Patent number: 11347912
    Abstract: The invention discloses a prediction method for porous material of electroacoustic devices and prediction system thereof. The method comprises the following steps. The step (A) is to obtain at least one acoustic parameter of a porous material from an electroacoustic device, and the at least one acoustic parameter comprises a flow resistance value, a specific flow resistance value and a flow resistance ratio. The step (B) is to calculate an actual resistance value of the porous material based on the at least one acoustic parameter. Thereafter, the step (C) establishes an equivalent circuit model corresponding to the electroacoustic device based on the structure configuration and material parameters of the electroacoustic device. At last, step (D) introduces the actual impedance value of the porous material into the equivalent circuit model, and calculates the frequency response curve and impedance curve of the electroacoustic device affected by the porous material.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 31, 2022
    Assignee: FENG CHIA UNIVERSITY
    Inventors: Yu-Cheng Liu, Jin-Huang Huang, Jui-Chu Weng, Tzu-Hsuan Lei
  • Patent number: 11320395
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Grant
    Filed: June 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Patent number: 11293897
    Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H. Chiang, Jui-Cheng Huang, Ke-Wei Su, Tung-Tsun Chen, Wei Lee, Pei-Wen Liu
  • Publication number: 20220091646
    Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Jui-Cheng HUANG, Yi-Hsing Hsiao, Yu-Jie Huang, Tsung-Tsun Chen, Allen Timothy Chang
  • Publication number: 20220065812
    Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG
  • Patent number: 11243184
    Abstract: Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: February 8, 2022
    Inventors: Yu-Jie Huang, Jui-Cheng Huang
  • Publication number: 20220033759
    Abstract: Cell monitoring apparatus includes sensing chip and channel module. Sensing chip includes channel region, source and drain regions, and sensing film. The channel region includes first semiconductor material. The source and drain regions are disposed at opposite sides of the channel region, and include a second semiconductor material. Sensing film is disposed on the channel region at a sensing surface of the sensing chip. Channel module is disposed on the sensing surface of sensing chip. A microfluidic channel is formed between the sensing surface of the sensing chip and a proximal surface of the channel module. The microfluidic channel includes a culture chamber and a micro-well. The culture chamber is concave into the proximal surface of the channel module, and overlies the channel region. The micro-well is concave into a side of the culture chamber, and directly faces the sensing film.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsing Hsiao, Jui-Cheng Huang
  • Patent number: 11209878
    Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng Huang, Yi-Hsing Hsiao, Yu-Jie Huang, Tsung-Tsun Chen, Allen Timothy Chang
  • Publication number: 20210399187
    Abstract: A circuit includes a thermoelectric structure and an energy device. The thermoelectric structure includes a wire and p-type and n-type regions positioned on a front side of a substrate, the wire configured to electrically couple the p-type region to the n-type region, a first via configured to thermally couple the p-type region to a first power structure on a back side of the substrate, and a second via configured to thermally couple the n-type region to a second power structure on the back side of the substrate. The energy device is electrically coupled to each of the first and second power structures.
    Type: Application
    Filed: March 16, 2021
    Publication date: December 23, 2021
    Inventors: Yu-Jie HUANG, Chung-Hui CHEN, Jui-Cheng HUANG, Tung-Tsun CHEN
  • Publication number: 20210389273
    Abstract: An integrated circuit device includes a device layer, an interconnect structure, a conductive layer, a passivation layer and a bioFET. The device layer has a first side and a second side and include source/drain regions and a channel region between the source/drain regions. The interconnect structure is disposed at the first side of the device layer. The conductive layer is disposed at the second side of the device layer. The passivation layer is continuously disposed on the conductive layer and the channel region and exposes a portion of the conductive layer. The bioFET includes the source/drain regions, the channel region and a portion of the passivation layer on the channel region.
    Type: Application
    Filed: June 14, 2020
    Publication date: December 16, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Jui-Cheng Huang, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Fu-Chun Huang
  • Publication number: 20210376091
    Abstract: A semiconductor device including: a first S/D arrangement including a silicide-sandwiched portion of a corresponding active region having a silicide-sandwiched configuration, a first portion of a corresponding metal-to-drain/source (MD) contact structure, a first via-to-MD (VD) structure, and a first buried via-to-source/drain (BVD) structure; a gate structure over a channel portion of the corresponding active region; and a second S/D arrangement including a first doped portion of the corresponding active region; and at least one of the following: an upper contact arrangement including a first silicide layer over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including a second silicide layer under the first doped portion, and a second BVD structure.
    Type: Application
    Filed: February 12, 2021
    Publication date: December 2, 2021
    Inventors: Chung-Hui CHEN, Tung-Tsun CHEN, Jui-Cheng HUANG
  • Publication number: 20210372962
    Abstract: Devices, methods for fabricating said devices, and methods for detecting an analyte within a bio-target are described herein. The device includes a top assembly and a bottom assembly. The Top assembly includes an electrode disposed on a top layer. The bottom assembly includes a bio-chip disposed on a bottom layer and a polymer body disposed between the bio-chip and the top assembly. The polymer body includes a channel. The electrode of the top assembly is positioned within the channel. The channel is configured to accommodate the bio-target containing the analyte.
    Type: Application
    Filed: January 4, 2021
    Publication date: December 2, 2021
    Inventors: Yi-Hsing Hsiao, Jui-Cheng Huang
  • Publication number: 20210349053
    Abstract: A bio-field effect transistor (bioFET) system includes a bioFET configured to receive a first voltage signal and output a current signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jie Huang, Jui-Cheng Huang
  • Publication number: 20210325338
    Abstract: A biosensor includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a FET device in the semiconductor layer, an isolation layer over the first surface of the semiconductor layer, a dielectric layer over the isolation layer and the first surface of the semiconductor layer, and a pair of first electrodes and a pair of second electrodes over the dielectric layer and separated from each other. The isolation layer has a rectangular opening substantially aligned with the FET device. The rectangular opening has pair of first sides and a pair of second sides. An extending direction of the pair of first sides is perpendicular to an extending direction of the pair of second sides. The pair of first electrodes is disposed over the pair of first sides, and the pair of second electrodes is disposed over the pair of second sides.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Inventors: YI-HSING HSIAO, JUI-CHENG HUANG, YU-JIE HUANG
  • Publication number: 20210325339
    Abstract: Biosensor devices and methods of forming the same are provided. A cavity is formed in a substrate and is configured to receive one or more charged molecules. A transistor is formed in the substrate and includes a source region, a drain region, and a channel region that are spatially separated from the cavity in a lateral direction. A gate of the transistor is disposed below the cavity and extends between the cavity and the source, drain, and channel regions. A voltage potential of the gate is based on a number of the charged molecules in the cavity.
    Type: Application
    Filed: May 10, 2021
    Publication date: October 21, 2021
    Inventors: Tung-Tsun Chen, Chien-Kuo Yang, Jui-Cheng Huang, Mark Chen, Ta-Chuan Liao, Cheng-Hsiang Hsieh
  • Patent number: 11137370
    Abstract: A sensor with a nanowire heater may be provided. The sensor may be patterned in a device layer of a Silicon on Insulation (SOI) wafer comprising a backside layer and a Buried Oxide (BOX) layer and the nanowire heater may be patterned in the device layer of the SOI wafer adjacent to the sensor. Next, metal routing may be created for the SOI wafer and a bond carrier wafer may be provided on a metal routing side of the SOI wafer. The backside layer may then be ground until the BOX layer is exposed. Then the device layer may be patterned through the BOX layer to expose the sensor and the nanowire heater. A dielectric may be deposited covering at least one of the following: the sensor; and the nanowire heater.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Allen Timothy Chang, Tung-Tsun Chen, Jui-Cheng Huang, Yu-Jie Huang, Yi-Hsing Hsiao
  • Patent number: 11119101
    Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 14, 2021
    Inventors: Jui-Cheng Huang, Chin-Hua Wen, Tung-Tsun Chen, Cheng-Hsiang Hsieh, Yu-Jie Huang, Ching-Hui Lin
  • Publication number: 20210263022
    Abstract: A fluidic cartridge and methods of operation are described. The fluidic cartridge includes a substrate having a plurality of contact pads designed to electrically couple with an analyzer, a semiconductor chip having a sensor array, and a reference electrode. The fluidic cartridge includes a first fluidic channel having an inlet and coupled to a second fluidic channel, the second fluidic channel being aligned such that the sensor array and the reference electrode are disposed within the second fluidic channel. A first plug is disposed at the first inlet. The first plug includes a compliant material configured to be punctured by a capillary without leaking fluid through the first plug.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Cheng HUANG, Chin-Hua WEN, Tung-Tsun CHEN, Cheng-Hsiang HSIEH, Yu-Jie HUANG, Ching-Hui LIN
  • Publication number: 20210239647
    Abstract: A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; a carrier substrate on the MLI structure; a first through substrate via (TSV) structure extending though the carrier substrate and configured to provide an electrical connection between the MLI structure and a separate die; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; and a microfluidic channel cap structure attached to the buried oxide layer.
    Type: Application
    Filed: November 11, 2020
    Publication date: August 5, 2021
    Inventors: Allen Timothy Chang, Jui-Cheng Huang, Wen-Chuan Tai, Yu-Jie Huang