Abstract: A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.

Abstract: A three-dimensional source contact structure and fabrication process method thereof are provided. A lithography process and shallow trench process are sequentially performed to form a metal contact window in a power device. A source heavily doped area is divided by the metal contact window into a first and second heavily doped region. A lateral etching process is applied to an inter-layer dielectric to form a first and a second dielectric layer, each of which is in a trapezoid shape. Meanwhile, a first and a second metal-source surface contact regions are exposed. A longitudinal surface exposed by the shallow trench process is beneficial to increase vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. The present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A three-dimensional source contact structure and its fabrication process method thereof are applicable to a power device, in which an inter-layer dielectric is deposited thereon. A lithography process is applied for forming a first and second dielectric layer. A spacer is respectively provided on opposite sidewalls of the first and second dielectric layer. And a shallow trench process is sequentially performed along the opposite surfaces of the spacers. The spacers are removed after the shallow trench process is complete for exposing a first and a second metal-source surface contact region. The present invention achieves in increasing horizontal surface contact and longitudinal vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. By employing the present invention, it enhances to reduce cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A process method for fabricating a three-dimensional source contact structure is provided, which is applicable to form a step-like three-dimensional source contact structure in a MOSFET of a power device. The proposed method sequentially adopts a lithography process and a shallow trench process to form a metal contact window. And a lateral etching process, or spacers which will be removed eventually, can be alternatively provided for increasing horizontal surface contact when depositing a source contact metal. Meanwhile, a longitudinal surface exposed by the shallow trench process is also beneficial to increase vertical contact when depositing the source contact metal. As a result, a step-like three-dimensional source contact structure can be formed by employing the present invention. It is believed that the present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

Abstract: A method for reducing parasitic junction field effect transistor resistance, applicable to a high power device having a semiconductor substrate layer, is provided, including providing a plurality of hard masks on a top surface of the semiconductor substrate layer. Each hard mask has a bottom plane and a tilt sidewall such that an acute angle is formed there in between. A body ion implantation process is subsequently performed, so a body region is formed between two adjacent hard masks. The body region has an upper and a lower surface. A width of the upper surface is greater than that of the lower surface. Therefore, the present invention achieves to control a parasitic JFET region characterized by having a wider bottom and a narrower top, thereby reducing its resistance thereof. Meanwhile, since a bottom angle of the body region is increased, breakdown voltage of the device is increased as well.

Abstract: A method for stabilizing breakdown voltages of floating guard ring, applicable to a high power device, is provided. The high power device has a semiconductor substrate layer, and at least one floating guard ring is formed at its termination. The method includes sequentially providing a pad oxide layer and barrier layer on an upper surface of the high power device to expose the floating guard ring, and then performing an ion implantation step. After removing the pad oxide layer and barrier layer, grow a field oxide layer, such that a defect layer is formed underneath. By employing the formed defect layer, the present invention achieves to control an interface potential level between the field oxide layer and the semiconductor substrate layer fixed at a certain potential value, without being affected by charges in the oxide layer or metal across over it, thereby stabilizing breakdown voltages of floating guard ring.

Abstract: A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.