Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A protection circuit for a power converter is provided. The protection circuit includes a sensor circuit, a detection circuit and an initial protection circuit. The sensor circuit senses an output current of the power converter to generate a load signal. The detection circuit detects a voltage signal at a signal terminal of the connection port. The initial protection circuit compares the load signal with an initial-protection threshold. When the voltage signal at the signal terminal switches to a high level from a low level after the protection circuit is enabled, the power converter enters an initial protection mode and the initial protection circuit counts an initial period of a port-identification procedure. When the load signal is larger than the initial-protection threshold during the initial period of the port-identification procedure, the initial protection circuit generates a first protection signal to shut down the power converter.

Abstract: A protection circuit for a power converter is provided. The protection circuit includes a sensor circuit, a detection circuit and an initial protection circuit. The sensor circuit senses an output current of the power converter to generate a load signal. The detection circuit detects a voltage signal at a signal terminal of the connection port. The initial protection circuit compares the load signal with an initial-protection threshold. When the voltage signal at the signal terminal switches to a high level from a low level after the protection circuit is enabled, the power converter enters an initial protection mode and the initial protection circuit counts an initial period of a port-identification procedure. When the load signal is larger than the initial-protection threshold during the initial period of the port-identification procedure, the initial protection circuit generates a first protection signal to shut down the power converter.

Abstract: A routing tool allows a user to create a set of routing templates, each specifying the shape of a routing corridor and identifying the corridor's terminal edges. Each routing template also specifies a set of constraints on routing of an unspecified number of conductors that are to be routed between the corridor's terminal edges. To direct the tool to create a routing plan for a particular set of conductors in a particular routing space, the user selects one of the routing templates and modifies the routing template if necessary to adjust the specified shape of the corridor to match that of the particular routing space or to adjust its specified routing constraints if necessary to accommodate any particular routing constraints to be imposed on that set of conductors. The routing tool then processes the modified routing template to generate the routing plan for routing the set of conductors between the terminal edges of the specified corridor in a manner that satisfies the specified routing constraints.

Abstract: A routing tool allows a user to create a set of routing templates, each specifying the shape of a routing corridor and identifying the corridor's terminal edges. Each routing template also specifies a set of constraints on routing of an unspecified number of conductors that are to be routed between the corridor's terminal edges. To direct the tool to create a routing plan for a particular set of conductors in a particular routing space, the user selects one of the routing templates and modifies the routing template if necessary to adjust the specified shape of the corridor to match that of the particular routing space or to adjust its specified routing constraints if necessary to accommodate any particular routing constraints to be imposed on that set of conductors. The routing tool then processes the modified routing template to generate the routing plan for routing the set of conductors between the terminal edges of the specified corridor in a manner that satisfies the specified routing constraints.

Abstract: In a computer-implemented method and system for creating a test component layout, after creating a reference component layout that is composed of a set of polygonal working shapes, a plurality of shape parameters are defined for the working shapes of the reference component layout, and a parameter template is formed based on the shape parameters of the reference component layout. Thereafter, user-defined distance values corresponding to the shape parameters may be inputted into the parameter template, and the test component layout is automatically created by adjusting geometry of the working shapes of the reference component layout with reference to the user-defined distance values inputted into the parameter template.

Abstract: In a computer-implemented method and system for creating a test component layout, after creating a reference component layout that is composed of a set of polygonal working shapes, a plurality of shape parameters are defined for the working shapes of the reference component layout, and a parameter template is formed based on the shape parameters of the reference component layout. Thereafter, user-defined distance values corresponding to the shape parameters may be inputted into the parameter template, and the test component layout is automatically created by adjusting geometry of the working shapes of the reference component layout with reference to the user-defined distance values inputted into the parameter template.

Abstract: In a rule-driven method and system for editing a physical integrated circuit layout formed from a plurality of working shapes, a desired one of the working shapes is initially created on a computer monitor. After calculating a width value associated with the desired one of the working shapes, the width value is verified to determine if it violates a minimum distance as defined by relevant design rules of an applied fabrication technology. Automatic adjustment of the geometry of the desired one of the working shapes to comply with the relevant design rules is subsequently performed upon verification that the width value violates the minimum distance.