Patents by Inventor Jui-Ching Hsieh

Jui-Ching Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip package structure and method of fabricating the same
    Patent number: 7989948
    Abstract: A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 2, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Jui-Ching Hsieh, Pin Chang, Chung-De Chen, Li-Chi Pan, Yu-Jen Wang, Chin-Horng Wang
  • CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20100139767
    Abstract: A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1.
    Type: Application
    Filed: May 26, 2009
    Publication date: June 10, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: Jui-Ching Hsieh, Pin Chang, Chung-De Chen, Li-Chi Pan, Yu-Jen Wang, Chin-Horng Wang