Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.

Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.

Abstract: A semiconductor package with MPS-C2 configuration is revealed, primarily comprising a substrate and a chip. A plurality of leads covered by a solder mask having a rectangular slot disposed on the top surface of the substrate to expose parts of the leads. A plurality of metal pillars are disposed on the active surface of the chip. A patterned plating layer is partially formed on the exposed portions of the leads located inside the slot to form a plurality of plating-defined fingers. Therefore, the soldering area of the solder on the leads can be constrained without exceeding the patterned plating layer to avoid issue of excessive solder ability.

Abstract: A disclosed semiconductor device having MPS-C2 (Metal Post Solder-Chip Connection) structure can be mounted on a PCB by an SMT mounter. A chip is disposed on a substrate. The substrate has a plurality of connecting pads and a plurality of accessory pads, and the chip has a plurality of corresponding metal posts and a plurality of accessory bumps. The dimensions on the soldered flat tops of the accessory bumps are corresponding to the soldered areas of the accessory pads where each soldered flat top has a plurality of angular corners and an edge between two adjacent angular corners where the length of the edge is twice greater than the pad pitch. Therefore, the displaced or rotational displaced metal posts can be pulled back and self-aligned during reflow processes so that an SMT mounter with poor alignment accuracy can be implemented for flip-chip bonding the semiconductor device having MPS-C2 structure to replace the conventional expensive flip-chip die bonder and to achieve higher productivity.