Abstract: A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.

Abstract: A system is provided. The system comprises a memory device and a test device. The test device that is operatively coupled to the memory device and transmits a plurality of glitch signals and a plurality of control signals after the plurality of glitch signals for a write operation of the memory device according to a data signal. The test device determines, based on write data of the data signal, whether read data outputted in a read operation of the memory device are bitwise shifted to generate a test result indicating a disturbance to the write operation induced by the plurality of glitch signals.

Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.