Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

Abstract: A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

Abstract: A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first plating through holes connected to first bonding pads and via the first insulating layer. A multi-layer structure is on the first insulating layer, which comprises conductive layout lines, second plating through holes therein, and a second insulating layer and exposed ball pads thereon. The first plating through holes are electrically connected with the conductive layout lines, the second plating through holes, and the exposed ball pads. A plurality of solder balls are affixed to the ball pads. Such architecture integrates the redistribution and fan-out process, which simplifies the conventional process for flip-chip ball grid array.

Abstract: A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

Abstract: The present invention provides a structure and a method for multi-chip stack package. The present invention uses the liquid insulating epoxy to adhere and stack chips. The liquid insulating epoxy is filled the space between chips and metal wires bonded thereon and the liquid insulating epoxy is higher than the high of the arc of those metal wires, so it can increase the reliability of stacking and bonding process. The present invention can stack multi-chip (more than two) by controlling the arc height of the wire and the thickness of the chip. The present can easily perform by visible equipment and materials.

Abstract: The present invention provides a structure and a method for multi-chip stack package. The present invention uses the liquid insulating epoxy to adhere and stack chips. The liquid insulating epoxy is filled the space between chips and metal wires bonded thereon and the liquid insulating epoxy is higher than the high of the arc of those metal wires, so it can increase the reliability of stacking and bonding process. The present invention can stack multi-chip (more than two) bycontrolling the arc height of the wire and the thickness of the chip. The present can easily perform by visible equipment and materials.

Abstract: The present invention provides a structure of a stacked-type multi-chip stack package of the leadframe. The shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).