Patents by Inventor Jui-Hei Huang

Jui-Hei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8580653
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Publication number: 20130171803
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
  • Patent number: 8404561
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Publication number: 20100291751
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 18, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
  • Patent number: 6719885
    Abstract: A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: April 13, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chun-Sheng Lin, Jui-Hei Huang, Chi-Sheng Lo, Long-Siang Chuang
  • Publication number: 20030165632
    Abstract: A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 4, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Sheng Lin, Jui-Hei Huang, Chi-Sheng Lo, Long-Siang Chuang