Abstract: A test method of an in-cell touch display device includes providing a plurality of first test signals and a plurality of second test signals to the first connection pads and the second connection pads of the in-cell touch display device, respectively. Each of the first connection pads is electrically connected to a corresponding data line of the in-cell touch display device, and each of the second connection pads is electrically connected to a corresponding touch electrode of the in-cell touch display device, and the in-cell touch display device is tested after the first and second test signals are provided to the first and second connection pads.

Abstract: An in-cell touch display device includes a first substrate, a second substrate, a plurality of scan lines, a plurality of data lines, a plurality of touch electrodes and a plurality of connection pads. The second substrate is disposed opposite to the first substrate. The scan lines and the data lines are disposed on the first substrate. The touch electrodes are disposed between the first substrate and the second substrate. The connection pads are disposed on the first substrate, and the connection pads are electrically connected to one of the data lines or one of the touch electrodes. Each of at least some of the connection pads has a bonding part and an extension part, and an area of the bonding part is smaller than an area of the extension part.

Abstract: A TFT array substrate includes gate lines, data lines, and first and second common lines. The gate lines are disposed on a transparent substrate. The first gate lines to the N+1-th gate lines are arranged in order, and N is a positive number. The data lines cross the gate lines. There is no pixel region defined by the N-th and N+1-th gate lines and adjacent two of the data lines, when N is an even number. There are two pixel regions being left and right pixel region defined by the N-th and N+1-th gate lines and adjacent two of the data lines, when N is an odd number. The first common lines are parallel to the gate lines. The second common lines are parallel to the data lines and electrically connected to the first common lines, wherein each second common line is disposed between the left and right pixel regions.

Abstract: A TFT array substrate includes gate lines, data lines, and first and second common lines. The gate lines are disposed on a transparent substrate. The first gate lines to the N+1-th gate lines are arranged in order, and N is a positive number. The data lines cross the gate lines. There is no pixel region defined by the N-th and N+1-th gate lines and adjacent two of the data lines, when N is an even number. There are two pixel regions being left and right pixel region defined by the N-th and N+1-th gate lines and adjacent two of the data lines, when N is an odd number. The first common lines are parallel to the gate lines. The second common lines are parallel to the data lines and electrically connected to the first common lines, wherein each second common line is disposed between the left and right pixel regions.