Abstract: A memory control method for adjusting sampling points utilized by a memory control circuit receiving a data signal and an original data strobe signal of a memory includes: utilizing at least one delay unit to provide a plurality of sampling points according to the original data strobe signal; sampling according to the data signal by utilizing the plurality of sampling points; and analyzing sampling results to dynamically determine a delay amount for delaying the original data strobe signal, whereby a sampling point corresponding to the delayed data strobe signal is kept centered at data carried by the data signal.

Abstract: A memory control method for adjusting deglitch windows utilized by a memory control circuit receiving an original data strobe signal of a memory includes: deglitching according to the original data strobe signal by utilizing a plurality of deglitch windows that are set by delaying an original deglitch window signal in order to derive a plurality of deglitch results, where the deglitch windows have different beginning time points; and utilizing the deglitch results to dynamically determine a delay amount for delaying the original deglitch window signal, where the beginning time point of one of the deglitch windows is kept centered at a middle time point of a preamble of the original data strobe signal.

Abstract: Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Abstract: An electronic system with time-sharing bus includes a controller, a storage element, a first electronic element, and a shared bus. The controller receives a command to generate a set of enable signals and a set of operation signals. The storage element has a first set of input ends coupled to the controller for receiving a first enable signal of the set of enable signals. The first electronic element has a first input end coupled to the controller for receiving a second enable signal of the set of enable signals. The shared bus is coupled between the controller and the storage element, and is coupled between the controller and the first electronic element. The shared bus provides the set of operation signals to the storage element while the first electronic element is disabled and provides the set of operation signals to the first electronic element while the storage element is disabled.

Abstract: Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

Abstract: A memory control method for adjusting sampling points utilized by a memory control circuit receiving a data signal and an original data strobe signal of a memory includes: utilizing at least one delay unit to provide a plurality of sampling points according to the original data strobe signal; sampling according to the data signal by utilizing the plurality of sampling points; and analyzing sampling results to dynamically determine a delay amount for delaying the original data strobe signal, whereby a sampling point corresponding to the delayed data strobe signal is kept centered at data carried by the data signal.

Abstract: A memory control method for adjusting deglitch windows utilized by a memory control circuit receiving an original data strobe signal of a memory includes: deglitching according to the original data strobe signal by utilizing a plurality of deglitch windows that are set by delaying an original deglitch window signal in order to derive a plurality of deglitch results, where the deglitch windows have different beginning time points; and utilizing the deglitch results to dynamically determine a delay amount for delaying the original deglitch window signal, where the beginning time point of one of the deglitch windows is kept centered at a middle time point of a preamble of the original data strobe signal.

Abstract: Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

Abstract: A memory system includes a first memory, a second memory, a determining unit, and an accessing unit. The capacity of the second memory is different from the capacity of the first memory. The first and the second memories are virtually partitioned into a first section and a second section. The determining unit determines to which of the first and the second sections an address corresponds, the address being associated with data to be transferred. The accessing unit is coupled to the determining unit and the first and second memories for transferring the data to or from the first memory and a first portion of the second memory when the determining unit determines that the address corresponds to the first section; and for transferring the data to or from a second portion of the second memory when the determining unit determines that the address corresponds to the second section.

Abstract: A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, coupled to the programmable delay module, for receiving the first and the second signals from the programmable delay module, and comparing a phase of a reference signal with phases of the first and the second signals, respectively; and a de-skew controlling module, coupled to the programmable delay module and the phase detecting module, for controlling the programmable delay module to eliminate imbalance between the first and the second signals by at least delaying the first signal according to a comparison result of the phase detecting module.

Abstract: A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit and the reference clock for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

Abstract: A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, coupled to the programmable delay module, for receiving the first and the second signals from the programmable delay module, and comparing a phase of a reference signal with phases of the first and the second signals, respectively; and a de-skew controlling module, coupled to the programmable delay module and the phase detecting module, for controlling the programmable delay module to eliminate imbalance between the first and the second signals by at least delaying the first signal according to a comparison result of the phase detecting module.

Abstract: Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. Varying a delay parameter until at least an edge of the internal clock signal and any edge of the read data signal are aligned. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Abstract: A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit and the refernce clock for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

Abstract: Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Abstract: A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.

Abstract: Methods and systems for generating a latch clock in memory reading. Data with a first logic level and with a second logic level are stored into a first address and a second address of a memory, respectively. A read data signal is generated by issuing continuous read commands for repeated retrieval of the data at the first and the second addresses of the memory. A divided frequency signal is generated by dividing a frequency of the internal clock. A phase of the divided frequency signal is adjusted according to a delay parameter by varying the delay parameter until at least an edge of the divided frequency signal is aligned with any edge of the read data signal. Finally, the latch clock is generated according to the delay parameter and the internal clock.

Abstract: A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrically coupled to the clock divider for delaying the frequency-divided clock to generate the delayed clock, a 180° phase detector electrically coupled to the programmable delay circuit for detecting a phase change of the delayed clock, and a delay lock loop controller electrically coupled to the programmable delay circuit and the 180° phase detector for programming the programmable delay circuit to lock the delayed clock according to the phase change.