Abstract: Devices and methods of fabricating devices are provided. One method includes: patterning an isolation gate disposed above a trench, the trench extending into a substrate; patterning a gate structure disposed above the substrate and adjacent the isolation gate; depositing a set of sidewall spacers on either side of the isolation gate and gate structure; etching a set of cavities between the isolation gate and gate structure and extending into the substrate; and epitaxially growing a set of epitaxial growths in the set of cavities, wherein the isolation gate is wider than the gate structure, and wherein epitaxial growths adjacent the isolation gate substantially conform to an oxide layer between the isolation gate and the trench, contacting at least a portion of a bottom surface and at least a portion of a side surface of the oxide layer.

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.