Abstract: The present application provides electronic devices and a data transmission method thereof for UniPro. The electronic device inserts a data length in a first symbol of a frame. Then, the electronic device transmits the first symbol to a peer electronic device and transmits at least one second symbol of the frame to the peer electronic device based on the data length. The peer electronic device receives the first symbol of the frame from the electronic device and receives the at least one second symbol of the frame from the electronic device based on the data length.

Abstract: A method and a controller for recovering data in event of a program failure and a storage system using the method and the controller are disclosed. The controller includes main units of a parity generator, a volatile memory module and a processor. With a parity in the volatile memory module and successfully programmed sub-data, a program failed write data can be recovered and correctly programmed. The method of the present invention has advantages of saving use of storage resources and extending lifetime of the storage system than other methods for recovering data in event of a program failure.

Abstract: A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

Abstract: A method and a controller for recovering data in event of a program failure and a storage system using the method and the controller are disclosed. The controller includes main units of a parity generator, a volatile memory module and a processor. With a parity in the volatile memory module and successfully programmed sub-data, a program failed write data can be recovered and correctly programmed. The method of the present invention has advantages of saving use of storage resources and extending lifetime of the storage system than other methods for recovering data in event of a program failure.

Abstract: An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended.

Abstract: A method for encoding multi-modes of BCH codes and an associated encoder is disclosed. The method has the steps of: building a number of encoding matrices; combining the encoding matrices with one side aligned to form a combined matrix; seeking common sub-expressions (CSEs) in the combined matrix, and encoding a message using the combined matrix.

Abstract: An early termination method with a re-encoding scheme for decoding of error correction codes is disclosed. The method includes the steps of: A. receiving soft values; B. processing hard decision on the soft value to determine a codeword; C. separating the codeword into a data part and a first parity part; D. re-encoding the data part to get a second parity part; E. checking if the first parity part and the second parity part are equivalent; and F. if a result of step E is yes, stopping decoding the codeword; if the result of step E is no, processing a decoding algorithm on the codeword. By this method, the received codeword still can be correctly decoded if there are many errors in the parity region and its decoding performance can be improved.

Abstract: A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

Abstract: The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The ith calculation unit operatively generates a second-bit-string by calculating ith bits of the n first-bit-strings. The jth shift unit operatively generates a third-bit-string upon receiving jth bits of the k second-bit-strings, and shifts the third-bit-string. The memory units are configured for storing the n shifted third-bit-strings respectively.

Abstract: A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a codeword, encoded by a first coding and a second coding sequentially; setting a maximum syndrome weight; decoding the second coding for the codeword by iterative calculations for syndromes; terminating decoding of the second coding if a number of the iterative calculations reaches a preset number or a syndrome weight of one iterative calculation is equal to or smaller than the maximum syndrome weight, otherwise repeating the decoding step and the terminating step; and decoding the first coding for the codeword.

Abstract: The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

Abstract: A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Abstract: A serial multiply accumulator (MAC) for operation of two multiplications and one addition over Galois field is disclosed. The MAC includes a first element feeding circuit, a second element feeding circuit, a number of first calculating circuits and a second calculating circuit. By re-arranging the circuit design, many elements used in the conventional MAC, such as XOR gates and registers, can be saved. The present invention has an advantage of lower area cost.

Abstract: The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. The determining bit is configured for operatively determining whether to continue decoding the encode data. Finally, when the determining bit is detected, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data.

Abstract: A decoder for A LDPC code and A BCH code and decoding method thereof are provided. The decoder decodes the encoded data based on the LDPC code and decodes the encoded data based on the BCH code simultaneously. Then the decoder outputs decoded data after the decoding procedure has been finished. Additionally, in the decoding procedure for decoding the encoded data based on the BCH code, the decoded result which the encoded data is decoded based on the LDPC code is utilized, so as to increase the processing speed for decoding the encoded data, and enhance the overall decoding performance.

Abstract: The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.

Abstract: A data format with ECC information for on-the-fly decoding during data transfer and method for forming the data format are disclosed. The method includes the steps of: dividing a parity check matrix having a message segment and a parity segment into a plurality of layers; choosing parity bit nodes in the parity segment of a first layer connected to check nodes; assembling the chosen parity bit nodes as a first parity segment and the rest parity bit nodes as a second parity segment; reallocating the parity check matrix so that the first parity segment is on the head of the message segment and the second parity segment is on the end of the message segment; forming a generating matrix according to the reallocated parity check matrix; and operating a message with the generating matrix to obtain the codeword.

Abstract: An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F?; building up F?; building up matrix of [XSRG F?]; and designing a circuit which fulfills the operation of [XSRG F?].

Abstract: The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. Finally, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data.

Abstract: An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended.