Abstract: A high speed wire end connector manufacturing method includes the following steps. First, a cable is soldered to a printed circuit board, and then an inner film is formed to cover a portion of the cable and a portion of the printed circuit board by an insert molding process. Another portion of the printed circuit board is passed through a guide hole of an outer casing, and a molded bonding layer is formed by an outer molding process to bond to the outer casing and the inner film. In addition, a metal spring latch is fixed on the outer casing. In addition, a high speed wire end connector is also disclosed herein.

Abstract: A high speed wire end connector manufacturing method includes the following steps. First, a cable is soldered to a printed circuit board, and then an inner film is formed to cover a portion of the cable and a portion of the printed circuit board by an insert molding process. Another portion of the printed circuit board is passed through a guide hole of an outer casing, and a molded bonding layer is formed by an outer molding process to bond to the outer casing and the inner film. In addition, a metal spring latch is fixed on the outer casing. In addition, a high speed wire end connector is also disclosed herein.

Abstract: A high speed wire end connector includes a printed circuit board, a cable, an inner film, an outer casing, and a molded bonding layer. The cable is soldered to the printed circuit board, the inner film covers a part of the cable and a part of the printed circuit board, and the outer casing is used to fix the printed circuit board, the cable and the printed circuit board, and a part of the printed circuit board is passed through a guide hole of the outer casing. The molded bonding layer bonds the outer casing to the inner film. In addition, a metal spring latch is mounted on the outer casing.

Abstract: A connector assembly includes a wire end connector for electrically connecting to a board end connector. The wire end connector includes a main body portion and an insertion portion. The insertion portion is connected to the main body portion, and the insertion portion is configured to couple to the board end connector. The main body portion is provided with a plurality of elastic claws extending outward from the main body portion to press on the board end connector when the insertion portion is coupled to the board end connector so as to stably connect the wire end connector to the board end connector.

Abstract: A device for fault detecting passive routing substrates. Thermal behavior differences before and after a passive routing substrate is damaged are used. A batch of passive routing substrates is fault detected without running a functional test. In addition, the passive routing substrates are not contacted and are not damaged on detection. The device provides superior and precise detection before stacking the passive routing substrates.

Abstract: A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.

Abstract: A device is provided for detecting passive routing substrates. Thermal behavior deference before and after an passive routing substrate is damaged is used. Thus, a batch of passive routing substrates can be detected. The present invention does not run functional test. In addition, the passive routing substrates are not contacted and would not be damaged on detection. Thus, the present invention is used for superior and precise detection before stacking the passive routing substrates.

Abstract: A stress relief structure is provided. The stress relief structure includes a stress relief body, at least one first stress relief base and at least one second stress relief base. The stress relief body has an upper surface and a lower surface opposite to each other. The first stress relief base is disposed on the upper surface of the stress relief body. The second stress relief base is disposed on the lower surface of the stress relief body. The at least one first stress relief base and the at least one second stress relief base are interlaced to each other.

Abstract: The disclosure provides an interposer testing device for testing an interposer and a method thereof which includes a heat source, a thermal image capturing device and a comparing device. The heat source is adapted for heating an area to be tested on the interposer. The thermal image capturing device is adapted for capturing a thermal image of the interposer after the interposer is heated. The comparing device is adapted for comparing the thermal image with a standard thermal image to output a comparison result.

Abstract: A stress relief structure is provided. The stress relief structure includes a stress relief body, at least one first stress relief base and at least one second stress relief base. The stress relief body has an upper surface and a lower surface opposite to each other. The first stress relief base is disposed on the upper surface of the stress relief body. The second stress relief base is disposed on the lower surface of the stress relief body. The at least one first stress relief base and the at least one second stress relief base are interlaced to each other.

Abstract: The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV.

Abstract: A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.

Abstract: A remote humidity monitor system for detecting a targeted object utilizes a humidity sensor to detect humidity and sends a result to a reader via the wireless communication device; a server can execute monitor management. The humidity sensor can be a mass hygrometer, an optical condensation dew-point hygrometer, a psychrometer (wet-and-dry bulb thermometer), a hair hygrometer, an electrolysis humidity sensor, a lithium chloride humidity sensor, an aluminum oxide humidity sensor, a high polymer humidity sensor, or an infrared hygrometer.