Abstract: A user gesture behavior simulation system includes a touch gesture recording and editing device and a touch gesture simulation device. When at least one touch gesture is implemented on a record touch object with at least one finger of a user, the at least one touch gesture is recorded by the touch gesture recording and editing device, and at least one touch gesture operating trajectory is correspondingly generated by the touch gesture recording and editing device. The touch gesture simulation device includes at least one artificial finger. The at least one artificial finger is driven and moved to an under-test touch object by the touch gesture simulation device. The at least one touch gesture is simulated by the touch gesture simulation device according to the at least one touch gesture operating trajectory.

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: An embossed porous membrane wipe and/or a method of making and/or using such embossed microporous membrane wipe. The preferred embossed microporous membrane wipe includes a microporous membrane embossed alone or with a polypropylene nonwoven. The nonwoven may be a spunbond, meltblown, and/or electrospun nonwoven. The microporous membrane may include a biaxially oriented microporous membrane. The biaxially oriented microporous membrane may be made from one or more block copolymers of polyethylene and/or polypropylene. A method of using such an embossed microporous membrane, composite or laminate wipe for skin oil blotting is also provided.

Abstract: An embossed porous membrane wipe and/or a method of making and/or using such embossed microporous membrane wipe. The preferred embossed microporous membrane wipe includes a microporous membrane embossed alone or with a polypropylene nonwoven. The nonwoven may be a spunbond, meltblown, and/or electrospun nonwoven. The microporous membrane may include a biaxially oriented microporous membrane. The biaxially oriented microporous membrane may be made from one or more block copolymers of polyethylene and/or polypropylene. A method of using such an embossed microporous membrane, composite or laminate wipe for skin oil blotting is also provided.

Abstract: A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics.

Abstract: A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics.

Abstract: A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.

Abstract: A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.