Patents by Inventor Jui-I Yu

Jui-I Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7816252
    Abstract: A method for forming a bump on under bump metallurgy according to the present invention is provided. A bonding pad is first formed on the active surface of a wafer. Subsequently, a passivation layer is formed on the active surface of the wafer and exposes the bonding pad. An under bump metallurgy is formed on the bonding pad. A layer of film is formed on the passivation layer and overlays the under bump metallurgy. Afterward, the portion of the film on the under bump metallurgy is exposed to a UV light and the exposed portion of the film is removed to expose the under bump metallurgy. A solder paste is applied to the under bump metallurgy and the remaining film on the wafer is removed. Finally, the solder paste is reflowed to form a spherical bump.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: October 19, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jui I Yu, Li Cheng Tai
  • Patent number: 7800240
    Abstract: An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: September 21, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Jui-I Yu
  • Patent number: 7518241
    Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 14, 2009
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
  • Publication number: 20090061614
    Abstract: A method for forming a bump on under bump metallurgy according to the present invention is provided. A bonding pad is first formed on the active surface of a wafer. Subsequently, a passivation layer is formed on the active surface of the wafer and exposes the bonding pad. An under bump metallurgy is formed on the bonding pad. A layer of film is formed on the passivation layer and overlays the under bump metallurgy. Afterward, the portion of the film on the under bump metallurgy is exposed to a UV light and the exposed portion of the film is removed to expose the under bump metallurgy. A solder paste is applied to the under bump metallurgy and the remaining film on the wafer is removed. Finally, the solder paste is reflowed to form a spherical bump.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jui I. YU, Li Cheng Tai
  • Publication number: 20080308938
    Abstract: An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold.
    Type: Application
    Filed: May 9, 2008
    Publication date: December 18, 2008
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Jui-I Yu
  • Publication number: 20070045848
    Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 1, 2007
    Inventors: Li-Cheng Tai, Jui-I Yu, Jiunn Chen, Chueh-An Hsieh, Shyh-Ing Wu, Shih-Kuang Chen, Tsung-Chieh Ho, Tsung-Hua Wu
  • Publication number: 20040259345
    Abstract: A formation method for a conductive bump is provided. A semiconductor structure has a conductive surface thereon. A photo resist layer is formed first and then removed in part to have an under-cut opening exposing the conductive surface. An under-bump-metallurgy layer is formed on the exposed conductive surface and the photo resist layer exclusive of the sidewall of the under-cut opening, and then a conductive material is subsequently formed on the under-bump-metallurgy layer and is then reflowed to form a conductive bump. Finally, the photo resist layer and the under-bump-metallurgy layer thereon are removed. The configuration feature of under-cut photo resist layer provides the disconnected formation of the under bump metallurgy structure, thus the whole manufacture process is simplified and the manufacture cost reduces.
    Type: Application
    Filed: June 10, 2004
    Publication date: December 23, 2004
    Inventors: Jui-I Yu, Feng-Cheng Tai