Abstract: A system and method for resolving the blank screen issue when switching between graphics processing units. The system and method provide a graphics adapter LCD timing controller (Tcon) with a frame buffer specifically dedicated to storing previously presented screen data for use when switching graphic processing units. The system further includes a protocol comparator unit within a serial-to-parallel converter and a memory controller coupled to the protocol comparator.

Abstract: An image capturing device includes a camera housing configured to house a set of electronic modules for generating a video stream from captured light. The camera housing includes a camera opening configured to let light enter the camera housing to be captured by the set of electronic modules. The webcam further includes a camera-housing base rotationally coupled to the camera housing, and includes a mounting base rotationally coupled to the camera-housing base. The camera housing is configured to rotate with respect to the camera-housing base to face the camera opening toward the mounting base or face the camera housing opening away from the mounting base. The webcam further includes a first hinge rotationally coupling the mounting base to the camera-housing base. With the camera opening facing toward the mounting base, the first hinge is configured such that the mounting base is foldable onto the camera opening to cover the camera opening.

Abstract: An image capturing device includes a camera housing configured to house a set of electronic modules for generating a video stream from captured light. The camera housing includes a camera opening configured to let light enter the camera housing to be captured by the set of electronic modules. The webcam further includes a camera-housing base rotationally coupled to the camera housing, and includes a mounting base rotationally coupled to the camera-housing base. The camera housing is configured to rotate with respect to the camera-housing base to face the camera opening toward the mounting base or face the camera housing opening away from the mounting base. The webcam further includes a first hinge rotationally coupling the mounting base to the camera-housing base. With the camera opening facing toward the mounting base, the first hinge is configured such that the mounting base is foldable onto the camera opening to cover the camera opening.

Abstract: A method for managing an alternating current adaptor system is disclosed. A direct current voltage is received at a high impedance power delivery network from a primary side of an alternating current adaptor system. An isolated voltage is output from the high impedance power delivery network to components of a secondary side of the alternating current adaptor system. A transition in a power state identification of an information handling system associated with the alternating current adaptor system is detected. An output voltage level of the alternating current adaptor system is alternated in response to the transition in the power state identification of the information handling system.

Abstract: A method for reducing current leakage in a battery in communication with an information handling system (IHS) is disclosed herein. The method includes providing a battery management unit (BMU) in the battery, the BMU in communication with an embedded controller, wherein the BMU comprises a detector pin. The method further includes placing the BMU in a standby mode to disable power from the battery to the IHS while the battery is coupled to the IHS, and configuring the BMU to exit the standby mode, if an external power supply is coupled to the IHS, to enable battery power from the battery to the IHS. Also disclosed is an information handling system (IHS) which includes an embedded controller operable to initiate a power-on sequence in the IHS, and a battery having a battery management unit (BMU), wherein the BMU is initially placed in a standby mode to disable battery power to the IHS, the BMU in communication with the embedded controller.

Abstract: A light emitting diode (LED) lamp. Brightness of the LED lamp is controlled by a dimmer and an external alternating current (AC) source is received via the dimmer. The LED lamp includes at least one LED, a rectifying-modulating-driving apparatus and a current holding compensator. The rectifying-modulating-driving apparatus is coupled between the LED and the dimmer for bridge-rectifying and modulating an AC source with a conducting angle from the dimmer to drive the LED. The current holding compensator is coupled to the rectifying-modulating-driving apparatus to provide a compensation current when the AC source with the conducting angle is lower than a voltage after being bridge-rectified.

Abstract: Methods and systems are described for utilizing multi-mode dongles with peripheral devices. The multi-mode dongles are configured to provide standard mode signals for a standard mode of operation and alternate mode signals for an alternate mode of operation, for example, where a host information handling system is unable to provide the alternate mode signals to the peripheral device. The multi-mode dongle receives mode control signals from a host information handling system and automatically switches from a standard mode of operation to an alternate mode of operation, where the alternate mode signals are provided to the peripheral device, based upon the mode control signals. In one embodiment, the multi-mode dongle can be configured for a universal serial bus (USB) port, and the alternate mode signals can be associated with charging a consumer electronics (CE) device.

Abstract: Phosphatidylinositol (PI) 3 kinase inhibitor compounds, their pharmaceutically acceptable salts, and prodrugs thereof; compositions of the new compounds, either alone or in combination with at least one additional therapeutic agent, with a pharmaceutically acceptable carrier; and uses of the new compounds, either alone or in combination with at least one additional therapeutic agent, in the prophylaxis or treatment of proliferative diseases characterized by the abnormal activity of growth factors, protein serine/threonine kinases, phospholipid kinases, G-protein coupled receptors, and phosphatases.

Abstract: A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure. Thereafter, an etching process is performed to remove a portion of the spacer material layer so that spacers are formed on the respective sidewalls of the gate structure. After that, a plasma treatment step is performed to form a spacer protection layer on the surface of the substrate, the spacers and the gate structure.

Abstract: A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure. Thereafter, an etching process is performed to remove a portion of the spacer material layer so that spacers are formed on the respective sidewalls of the gate structure. After that, a plasma treatment step is performed to form a spacer protection layer on the surface of the substrate, the spacers and the gate structure.

Abstract: A method of manufacturing a spacer for a substrate having a gate structure formed thereon. The method comprises steps of forming a first oxide layer over the substrate and forming a nitride layer on the first oxide layer. A first asymmetric etching process is performed to remove a portion of the nitride layer until a portion of a top surface of the first oxide layer is exposed. A second asymmetric etching process is performed to remove a portion of the first oxide layer by using the remaining nitride layer as a mask until about 50% to 90% portion of the first oxide layer is removed. A quick wet etching process is performed to remove a portion of the remaining first oxide located on the top of the gate structure and on the substrate.

Abstract: A method of fabricating spacers is provided. The method includes providing a substrate with a device structure formed thereon. The device structure comprises a gate structure and a pair of source/drain regions. Then, a spacer material layer is formed over the substrate to cover the substrate and the device structure. Thereafter, an etching process is performed to remove a portion of the spacer material layer so that spacers are formed on the respective sidewalls of the gate structure. After that, a plasma treatment step is performed to form a spacer protection layer on the surface of the substrate, the spacers and the gate structure.

Abstract: A method of manufacturing a spacer for a substrate having a gate structure formed thereon. The method comprises steps of forming a first oxide layer over the substrate and forming a nitride layer on the first oxide layer. A first asymmetric etching process is performed to remove a portion of the nitride layer until a portion of a top surface of the first oxide layer is exposed. A second asymmetric etching process is performed to remove a portion of the first oxide layer by using the remaining nitride layer as a mask until about 50% to 90% portion of the first oxide layer is removed. A quick wet etching process is performed to remove a portion of the remaining first oxide located on the top of the gate structure and on the substrate.

Abstract: The present invention provides a metal-oxide semiconductor (MOS) transistor that functions as a rectifier positioned on a semiconductor wafer. The semiconductor wafer comprises a substrate, an active area defined on the substrate, a second P-type well positioned on the active area of the substrate and a field oxide layer positioned on the substrate which surrounds the active area. The MOS transistor comprises an N-type well positioned within a first predetermined area of the active area, a first P-type well positioned within the N-type well, a first N-type doped region positioned within the first P-type well, a second N-type doped region positioned within a second predetermined area of the active area, the second predetermined area not overlapping the first predetermined area, and a gate layer positioned on the substrate between the first N-type doped region and the second N-type doped region.

Abstract: A method and apparatus for reducing particle contamination on wafers is disclosed. The method includes providing a semiconductor furnace system having an ideal reaction chamber, an electrostatic generator, a conducting wire, and a conductive ring. Moreover, an insulating layer is coated over the entire wafer boat carrier, that is part of the reaction chamber. Charges with a first polarity are generated after a reaction process carried out inside the chamber and before the “vacuum breaking” stage. These charges spread evenly across the entire exposed surface of the wafer boat carrier and repulse particles carrying the same polarity away from the wafers that are in process.

Abstract: A drafting apparatus in a furnace. A buffer board having a plurality of gas intakes is disposed in a front end of the drafting apparatus. A laminar flow board having a plurality of gas outtakes is disposed in a rear end of the drafting apparatus. A drafting region is enclosed by the drafting apparatus. The drafting region comprises at least one drafting board to draft and redirect the gas flow. A laminar flow is then obtained to flow through the outtakes on the laminar board.

Abstract: A buried wiring line. The structure of the buried wiring line at least comprises a conductive doped region in a provided substrate and a silicon nitride region formed around the conductive doped region in the substrate. The silicon nitride region, which comprises a first silicon nitride below the doped region and a second silicon nitride layer beside the doped region, isolates the buried wiring line from the substrate.

Abstract: A method for removing sediments under sewage water in a sewer includes: introducing a portion of a cable into a sewer from the ground by extending the cable into the sewer through an inlet in the ground accessible to the sewer and out of the sewer through an outlet in the ground communicated with the sewer; lowering the portion of the cable until the portion of the cable is embedded in the sediments; positioning two ends of the cable extending outwardly of the inlet and the outlet on the ground; moving mechanically the cable to stir and suspend the sediments into the sewage water; pumping the suspended sediments from the sewer to the ground through one of the inlet and the outlet; removing the sediments from the sewage water by filtration on the ground; and returning the sewage water to the sewer through the other one of the inlet and the outlet.

Abstract: The present invention provides a method for enhancing the reliability of a dielectric layer of a semiconductor wafer. The dielectric layer is formed above a silicon element. First, the method implants argon ions with a dosage of around 1015˜1016 ions/cm3 and an energy of around 3˜50 KeV into the silicon element to form an ion implantation layer. Then, the dielectric layer is formed on a predetermined area of the silicon element. The ion implantation layer prevents oxygen ions, impurities and charge carriers from converging on the surface of the silicon element so as to enhance the reliability of the dielectric layer.

Abstract: The invention relates to a method of forming a stack-gate of a non-volatile memory. In this method, the stack-gate is formed in a predetermined region of the substrate of a semiconductor wafer. Then, a gate oxide layer, a first gate conductive layer, a dielectric layer, and a passivation layer are formed followed by lithography and stripping of the photo-resist layer and removal of the passivation layer from the dielectric layer. Finally, a second gate conductive layer is formed on the dielectric layer as the control gate of the stack-gate. The passivation layer can prevent the dielectric layer from being damaged during stripping of the photo-resist layer.