Patents by Inventor Jui-Ming Chen
Jui-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12388252Abstract: The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.Type: GrantFiled: March 20, 2023Date of Patent: August 12, 2025Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Chien-Ming Hsu, Jui-Ming Chen
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Publication number: 20240364339Abstract: An interface device includes a dynamic tracking bias circuit, an ESD (Electrostatic Discharge) clamp circuit, a pre-driver, a post-driver, and an I/O (Input/Output) pad. The dynamic tracking bias circuit provides a first supply voltage. The first supply voltage is determined according to a main power voltage and a second supply voltage. The ESD clamp circuit limits the second supply voltage. The post-driver is driven by the pre-driver. The I/O pad is driven by the post-driver. The pre-driver and the post-driver are supplied by the main power voltage, the first supply voltage, and the second supply voltage.Type: ApplicationFiled: March 25, 2024Publication date: October 31, 2024Inventors: Yu-Shen LIN, Jui-Ming CHEN, Federico Agustin ALTOLAGUIRRE
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Patent number: 12006733Abstract: A door lock device is provided and includes: a lock assembly having a first lock structure and a second lock structure; an acting assembly interlocked with the first lock structure and the second lock structure; and an operation assembly interlocked with the acting assembly so as to unlock the first lock structure and the second lock structure synchronously. Therefore, when the lock assembly is in the form of top and bottom locks, the top and bottom locks can be unlocked at the same time, so as to allow an escape door to be opened quickly, thereby facilitating emergency escape.Type: GrantFiled: October 7, 2020Date of Patent: June 11, 2024Assignee: THASE ENTERPRISE CO., LTD.Inventors: Jui-Ming Chen, Ching-Tien Lin
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Publication number: 20230327428Abstract: The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.Type: ApplicationFiled: March 20, 2023Publication date: October 12, 2023Applicant: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Chien-Ming Hsu, Jui-Ming Chen
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Patent number: 11753851Abstract: A lock assembly is provided and includes: a driving member; an acting member connected to the driving member; an active member cooperating with the acting member for operation; and a main lock member interlocked with the active member. The driving member drives the acting member to swing and the acting member touches the active member so as to displace the active member and synchronously displace the main lock member. Therefore, the lock assembly is buried in a door frame through cooperation of the driving member, the acting member and the active member, so as to be protected from being damaged or stolen.Type: GrantFiled: July 22, 2020Date of Patent: September 12, 2023Assignee: THASE ENTERPRISE CO., LTDInventors: Jui-Ming Chen, Ching-Tien Lin
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Patent number: 11716073Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: GrantFiled: January 21, 2022Date of Patent: August 1, 2023Assignee: MEDIATEK INC.Inventors: Hsin-Cheng Hsu, Jui-Ming Chen, Federico Agustin Altolaguirre
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Patent number: 11655655Abstract: A door lock device is provided and includes a lock assembly and an operation assembly interlocked with the lock assembly so as to bury the lock assembly in a door frame, thereby protecting the lock assembly from being damaged or stolen.Type: GrantFiled: July 22, 2020Date of Patent: May 23, 2023Assignee: THASE ENTERPRISE CO., LTD.Inventors: Jui-Ming Chen, Ching-Tien Lin
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Patent number: 11588106Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.Type: GrantFiled: October 27, 2020Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
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Publication number: 20220329232Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.Type: ApplicationFiled: January 21, 2022Publication date: October 13, 2022Inventors: Hsin-Cheng HSU, Jui-Ming CHEN, Federico Agustin ALTOLAGUIRRE
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Publication number: 20210285260Abstract: A door lock device is provided and includes: a lock assembly having a first lock structure and a second lock structure; an acting assembly interlocked with the first lock structure and the second lock structure; and an operation assembly interlocked with the acting assembly so as to unlock the first lock structure and the second lock structure synchronously. Therefore, when the lock assembly is in the form of top and bottom locks, the top and bottom locks can be unlocked at the same time, so as to allow an escape door to be opened quickly, thereby facilitating emergency escape.Type: ApplicationFiled: October 7, 2020Publication date: September 16, 2021Applicant: THASE ENTERPRISE CO., LTD.Inventors: Jui-Ming Chen, Ching-Tien Lin
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Publication number: 20210277687Abstract: A door lock device is provided and includes a lock assembly and an operation assembly interlocked with the lock assembly so as to bury the lock assembly in a door frame, thereby protecting the lock assembly from being damaged or stolen.Type: ApplicationFiled: July 22, 2020Publication date: September 9, 2021Inventors: Jui-Ming CHEN, Ching-Tien LIN
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Publication number: 20210277708Abstract: A lock assembly is provided and includes: a driving member; an acting member connected to the driving member; an active member cooperating with the acting member for operation; and a main lock member interlocked with the active member. The driving member drives the acting member to swing and the acting member touches the active member so as to displace the active member and synchronously displace the main lock member. Therefore, the lock assembly is buried in a door frame through cooperation of the driving member, the acting member and the active member, so as to be protected from being damaged or stolen.Type: ApplicationFiled: July 22, 2020Publication date: September 9, 2021Inventors: Jui-Ming CHEN, Ching-Tien LIN
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Publication number: 20210066590Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.Type: ApplicationFiled: October 27, 2020Publication date: March 4, 2021Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
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Patent number: 10862031Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.Type: GrantFiled: March 1, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
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Publication number: 20200279998Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Yu Chao Lin, Jui-Ming Chen, Shao-Ming Yu, Tung Ying Lee, Yu-Sheng Chen
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Patent number: 9613819Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.Type: GrantFiled: June 6, 2014Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
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Publication number: 20150357164Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
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Publication number: 20080095446Abstract: A method and system for performing image processing in a computer apparatus. The system has an image driver unit to receive a video stream output by an image capture device and perform a pre-processing on the video stream to thereby obtain a color video stream, and an image processing module to use an application programming interface (API) to notify the image driver unit of outputting the color video stream in order to perform a special effect processing on the color video stream to thereby produce a processed video stream. The image processing module uses another API to notify the image driver unit and send the processed video stream to the image driver unit. The image driver unit performs a post-processing on the processed video stream. Accordingly, the image processing module can use the resources of a user mode to perform the complicated image processing operations.Type: ApplicationFiled: October 19, 2007Publication date: April 24, 2008Applicant: Sunplus Technology Co., Ltd.Inventors: Jui-Ming Chen, Li-Ming Chen, Ji-Jeng Deng
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Patent number: 7315750Abstract: The present invention provides a method and system for selecting an access network in a heterogeneous network environment. The method records user configuration information in a mobile device and applies the mobile device to first collect and record current status information of each access network, then determines a network stability coefficient for each access network based on both the user configuration information and the current status information, and finally selects an access network with a maximum network stability coefficient to thus establish a connection with the access network selected.Type: GrantFiled: February 2, 2005Date of Patent: January 1, 2008Assignee: Industrial Technology Research InstituteInventors: Li-Der Chou, Jui-Ming Chen, Ju-Wei Chen, Jen-Shun Yang
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Publication number: 20060030319Abstract: The present invention provides a method and system for selecting an access network in a heterogeneous network environment. The method records user configuration information in a mobile device and applies the mobile device to first collect and record current status information of each access network, then determines a network stability coefficient for each access network based on both the user configuration information and the current status information, and finally selects an access network with a maximum network stability coefficient to thus establish a connection with the access network selected.Type: ApplicationFiled: February 2, 2005Publication date: February 9, 2006Applicant: Industrial Technology Research InstituteInventors: Li-Der Chou, Jui-Ming Chen, Ju-Wei Chen, Jen-Shun Yang