Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.

Abstract: In some examples, a device can include a locking mechanism to couple the device to a computing device enclosure, a first portion at a first level to interact with a processor back-plate, and a second portion at a second level to interact with an area proximate to the processor back-plate, wherein the second portion protrudes to the second level toward the processor back-plate when the device is coupled to the computing device enclosure.

Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.

Abstract: The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.

Abstract: A lock assembly is provided and includes: a driving member; an acting member connected to the driving member; an active member cooperating with the acting member for operation; and a main lock member interlocked with the active member. The driving member drives the acting member to swing and the acting member touches the active member so as to displace the active member and synchronously displace the main lock member. Therefore, the lock assembly is buried in a door frame through cooperation of the driving member, the acting member and the active member, so as to be protected from being damaged or stolen.

Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

Abstract: A door lock device is provided and includes a lock assembly and an operation assembly interlocked with the lock assembly so as to bury the lock assembly in a door frame, thereby protecting the lock assembly from being damaged or stolen.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.

Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

Abstract: A door lock device is provided and includes: a lock assembly having a first lock structure and a second lock structure; an acting assembly interlocked with the first lock structure and the second lock structure; and an operation assembly interlocked with the acting assembly so as to unlock the first lock structure and the second lock structure synchronously. Therefore, when the lock assembly is in the form of top and bottom locks, the top and bottom locks can be unlocked at the same time, so as to allow an escape door to be opened quickly, thereby facilitating emergency escape.

Abstract: A door lock device is provided and includes a lock assembly and an operation assembly interlocked with the lock assembly so as to bury the lock assembly in a door frame, thereby protecting the lock assembly from being damaged or stolen.

Abstract: A lock assembly is provided and includes: a driving member; an acting member connected to the driving member; an active member cooperating with the acting member for operation; and a main lock member interlocked with the active member. The driving member drives the acting member to swing and the acting member touches the active member so as to displace the active member and synchronously displace the main lock member. Therefore, the lock assembly is buried in a door frame through cooperation of the driving member, the acting member and the active member, so as to be protected from being damaged or stolen.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.

Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.

Abstract: A method and system for performing image processing in a computer apparatus. The system has an image driver unit to receive a video stream output by an image capture device and perform a pre-processing on the video stream to thereby obtain a color video stream, and an image processing module to use an application programming interface (API) to notify the image driver unit of outputting the color video stream in order to perform a special effect processing on the color video stream to thereby produce a processed video stream. The image processing module uses another API to notify the image driver unit and send the processed video stream to the image driver unit. The image driver unit performs a post-processing on the processed video stream. Accordingly, the image processing module can use the resources of a user mode to perform the complicated image processing operations.

Abstract: The present invention provides a method and system for selecting an access network in a heterogeneous network environment. The method records user configuration information in a mobile device and applies the mobile device to first collect and record current status information of each access network, then determines a network stability coefficient for each access network based on both the user configuration information and the current status information, and finally selects an access network with a maximum network stability coefficient to thus establish a connection with the access network selected.