Abstract: An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

Abstract: In a dual damascene process for forming a multi-layer low-k dielectric interconnect, the formation of each layer of interconnect comprises deposition of a first low-k dielectric layer, etching of the first low-k dielectric layer to form two dual damascene vias, formation of two Cu conductor plugs enclosed with barrier layers in the two dual damascene vias, etching of the first low-k dielectric layer between the two dual damascene vias to form a trench, and spin-on of a second low-k dielectric layer filled in the trench. The spin-on low-k dielectric layer is selected to have a dielectric constant smaller than that of the first low-k dielectric layer to reduce the equivalent dielectric constant in the layer of interconnect.

Abstract: In a dual damascene process for forming a multi-layer low-k dielectric interconnect, the formation of each layer of interconnect comprises deposition of a first low-k dielectric layer, etching of the first low-k dielectric layer to form two dual damascene vias, formation of two Cu conductor plugs enclosed with barrier layers in the two dual damascene vias, etching of the first low-k dielectric layer between the two dual damascene vias to form a trench, and spin-on of a second low-k dielectric layer filled in the trench. The spin-on low-k dielectric layer is selected to have a dielectric constant smaller than that of the first low-k dielectric layer to reduce the equivalent dielectric constant in the layer of interconnect.

Abstract: In a dual damascene process for forming a multi-layer low-k dielectric interconnect, the formation of each layer of interconnect comprises deposition of a first low-k dielectric layer, etching of the first low-k dielectric layer to form two dual damascene vias, formation of two Cu conductor plugs enclosed with barrier layers in the two dual damascene vias, etching of the first low-k dielectric layer between the two dual damascene vias to form a trench, and spin-on of a second low-k dielectric layer filled in the trench. The spin-on low-k dielectric layer is selected to have a dielectric constant smaller than that of the first low-k dielectric layer to reduce the equivalent dielectric constant in the layer of interconnect.

Abstract: A re-oxidation process of a semiconductor device is described. A substrate having a stacked structure thereon is provided, wherein the stacked structure includes a polysilicon/tungsten silicide interface. A thin CVD oxide layer is formed on the substrate and the stacked structure with a chemical vapor deposition (CVD) process. Then, an oxidation process is performed to form a thermal oxide layer on the substrate and the stacked structure.

Abstract: A re-oxidation process of a semiconductor device is described. A substrate having a stacked structure thereon is provided, wherein the stacked structure includes a polysilicon/tungsten suicide interface. A thin CVD oxide layer is formed on the substrate and the stacked structure with a chemical vapor deposition (CVD) process. Then, an oxidation process is performed to form a thermal oxide layer on the substrate and the stacked structure.

Abstract: The present invention provides a metallization process of in-situ forming titanium nitride and tungsten nitride in a tungsten plug. In the present invention, a dielectric layer is formed on the surface of a substrate, a via hole is formed on the dielectric layer, and a titanium layer is deposited on the surfaces of the dielectric layer and the via hole. Next, a titanium nitride passivation, a barrier layer of tungsten nitride, and a tungsten plug are formed in turn on the titanium layer in the same chamber. Finally, part of the tungsten layer on the surface is removed to leave only the tungsten in the via hole. A tungsten plug is thus formed. The present invention can decrease the count of required chambers and reduce the production cost.

Abstract: A dual damascene semiconductor device (38) includes a first insulation layer (12) with a first electrical contact (14). A second insulation layer (20), having an outer surface (40), is formed over the first insulation layer and a trench (26) is preferably formed in the outer surface of the second insulation layer. The second insulation layer is a continuous, nonlayered layer of material. A second electrical contact (36) is embedded within the second insulation layer, typically within the trench. An electrical connection (34) passes through a via (hole) (32) formed in the second insulation layer to electrically connect the first and second electrical contacts. An etching-stop layer (18) may be used between the first and second insulation layers. The metal connection and electrical contacts may be made of copper. This invention applied the top surface image method to the via photo step.