Patents by Inventor Jui-Pin Chiu

Jui-Pin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791404
    Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: October 17, 2023
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
  • Patent number: 11411080
    Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: August 9, 2022
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu, She-Hsin Hsiao
  • Publication number: 20220216303
    Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU, She-Hsin HSIAO
  • Publication number: 20220020868
    Abstract: A bipolar transistor includes a substrate, a sub-collector layer, a collector layer, a base layer, an emitter layer, a passivation layer, and a collector electrode. The sub-collector layer is formed over the substrate. The collector layer is formed over the sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The passivation layer is formed over the substrate and covering a sidewall of the collector layer. The collector electrode is connected to the sub-collector layer through an opening in the passivation layer. The opening exposes at least a portion of the sub-collector layer.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU
  • Patent number: 11164962
    Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 2, 2021
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chien-Rong Yu, Shu-Hsiao Tsai, Jui-Pin Chiu
  • Publication number: 20210210626
    Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Inventors: Chien-Rong YU, Shu-Hsiao TSAI, Jui-Pin CHIU
  • Patent number: 10553709
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 4, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
  • Patent number: 10256329
    Abstract: A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising IniGa1-iAs with an Indium content i with a slope s1 and a second base layer on the emitter side comprising InjGa1-jAs with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising InmGa1-mAs with an Indium content m and a second base layer on the emitter side comprising InnGa1-nAs with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 9, 2019
    Assignee: Win Semiconductors Corp.
    Inventors: Shinichiro Takatani, Jui-Pin Chiu, Chia-Ta Chang
  • Publication number: 20180145159
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Jui-Pin CHIU, Shu-Hsiao TSAI, Rong-Hao SYU, Cheng-Kuo LIN
  • Patent number: 9911837
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: March 6, 2018
    Assignee: Win Semiconductors Corp.
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin
  • Publication number: 20170069739
    Abstract: A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising IniGa1-iAs with an Indium content i with a slope s1 and a second base layer on the emitter side comprising IniGa1-jAs with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising InmGa1-mAs with an Indium content m and a second base layer on the emitter side comprising InnGa1-nAs with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: SHINICHIRO TAKATANI, JUI-PIN CHIU, CHIA-TA CHANG
  • Publication number: 20160322482
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two recesses respectively on two opposite sides of the “H” shape, and the emitter has two elongated emitter electrodes formed on the “H” shaped emitter. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, and each of the base electrodes has a base via hole at or near the center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Jui-Pin CHIU, Shu-Hsiao TSAI, Rong-Hao SYU, Cheng-Kuo LIN
  • Publication number: 20160020307
    Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.
    Type: Application
    Filed: April 21, 2015
    Publication date: January 21, 2016
    Inventors: Jui-Pin Chiu, Shu-Hsiao Tsai, Rong-Hao Syu, Cheng-Kuo Lin