Abstract: An apparatus for forming a film on a wafer in the semiconductor process is provided. The apparatus includes an inner part containing a susceptor for mounting thereon the wafer, and an outer part covering the inner part. There are an inlet and an outlet between the inner part and the outer part and gases can flow in and out through them. A special gas-feeding pipe is partially mounted inside the inlet. The gases are ejected from the gas-feeding pipe and toward the outer part instead of the inner part. Hence, the temperature difference between the gases and the inner part is diminished and the film adhered to the inner part will not peel to form particles. It reduces the contamination problem. A gas-feeding method is also provided according to the present apparatus.

Abstract: A method of forming a STI structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.

Abstract: A method of forming a STI structure. First, a substrate having a trench is provided. Next, a conformable silicon oxide layer is grown on the surface of the trench by wet oxidation using single wafer process to serve as a liner oxide layer. Thereafter, the substrate and the silicon oxide layer is in-situ annealed. Finally, an insulating layer is completely filled into the trench.

Abstract: A chemical bath having liquid level indications in an outer trough is disclosed. The present invention adds an aqueduct in the outer bath of the chemical bath, and the chemical treatment liquid could flow into the aqueduct. According to the Pascal's law, the liquid level of the chemical treatment liquid in the aqueduct is the same with the liquid level of the chemical treatment liquid in the outer bath. Therefore, the level height of the chemical treatment liquid in the outer bath is observed from the transparent aqueduct by the naked eyes. The present invention abridges the complicated checkup steps, so that the producing time of apparatuses is increased and the amount of the wastes chemicals is decreased.

Abstract: The present invention, a method for decreasing wafer scrap rate in the chemical treatment apparatus, performs the controls of the robots, the drain valve of the chemical treatment bath and the supply valve of ultra-pure water to decrease the reaction rate between a wafer and the chemical treatment liquid, wherein the controls are performed in accordance with different abnormal factors, such as the abnormal conditions of power supply and the robots. The present invention can be used in the control system, such as by writing a recipe added to the control system. When an alarm occurs, the control system can execute the recipe to decrease the wafer damage. According to the present invention, the method for decreasing wafer scrap rate in the chemical treatment apparatus has the advantages of saving the wafer-manufacturing cost and increasing the wafer-manufacturing yield.

Abstract: A gate for preventing dopants from penetrating a gate insulator comprises a polysilicon layer and an amorphous-silicon layer disposing on the polysilicon layer. The layered gate inhibits dopants from penetrating through a gate oxide layer disposing between the gate and a substrate. A source and a drain are disposed in the substrate beside the amorphous-silicon layer and the polysilicon layer.

Abstract: A method of eliminating leakage current in shallow trench isolation is disclosed. After the trench is formed on the substrate, the liner oxide layer is formed in the furnace by introducing transdichloroethylene (TLC) into the furnace to round the corner of the trench. An electric filed near the rounded trench corner is decreased; thus, the leakage current produced in the corner of the shallow trench isolation is eliminated.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: A method for automatically adjusting a concentration of a solution having a first component and a second component, used in a semiconductor manufacturing process, includes the steps of (a) providing target concentrations of the first component and the second component, (b) adjusting the concentration of the solution based on the first component by adding a first spiking amount of the first component during a first spiking time interval, and (c) adjusting the first spiking amount of the first component until a first deviation between an actual concentration of the first component and the target concentration of the first component is smaller than a first specific percentage.

Abstract: A method for improving trench isolation is disclosed. A trench is etched into the substrate by using a photo mask. A bottom oxide layer, a sidewall oxide layer and a polycrystalline silicon layer are deposited into the trench and over the wafer, and are etched to clear from the surface, then over-etched till a recess is formed within the trench. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, an oxidation step is utilized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent stress problem induced by a wedge shaped oxide growing in the space between the plug and the substrate.

Abstract: An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.