Patents by Inventor Jui-Seng WANG

Jui-Seng WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942425
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Tsai, Jui-Seng Wang, Yi-Yi Chen
  • Patent number: 11903179
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Tsai, Jui-Seng Wang, Yi-Yi Chen
  • Publication number: 20240008266
    Abstract: The present application provides a method of fabricating bit line contacts. The method includes steps of depositing an insulative layer and a sacrificial layer on the substrate; forming a photosensitive layer on the sacrificial layer; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to form an intermediate pattern on the sacrificial layer; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to form a target pattern on the sacrificial layer; performing a first etching process to remove portions of the sacrificial layer exposed by the target pattern; performing a second etching process to form a plurality of trenches in the insulative layer; and depositing a conductive material into the plurality of trenches to form the bit line contacts.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20240004300
    Abstract: The present application provides a method of processing a substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20230335490
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Publication number: 20230337411
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: CHIH-YING TSAI, JUI-SENG WANG, YI-YI CHEN
  • Patent number: 11631585
    Abstract: A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 18, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jui-Seng Wang, Yu-Chen Huang
  • Publication number: 20220223414
    Abstract: A method for fabricating a semiconductor structure includes: providing a substrate and a dielectric layer on the substrate; and forming an etching mask on the dielectric layer; and etching the dielectric layer using the etching mask to form at least one opening therein. The etching mask includes: a hard mask layer, a photoresist layer, and a hexamethyldisilazane (HMDS) layer. The photoresist layer is located over the hard mask layer, and the HMDS layer is located between the hard mask layer and the photoresist layer.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 14, 2022
    Inventors: Jui-Seng WANG, Yu-Chen HUANG