Patents by Inventor Jui-Te Chan

Jui-Te Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6483751
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: November 19, 2002
    Assignee: Amic Technology
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Patent number: 6353556
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: March 5, 2002
    Assignee: AMIC Technology, Inc.
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Publication number: 20010015911
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Application
    Filed: April 24, 2001
    Publication date: August 23, 2001
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Patent number: 6249459
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: June 19, 2001
    Assignee: AMIC Technology, Inc.
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Patent number: 6219281
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: April 17, 2001
    Assignee: AMIC Technology, Inc.
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Patent number: 6198662
    Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: March 6, 2001
    Assignee: AMIC Technology, Inc.
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan
  • Patent number: 6166962
    Abstract: A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: December 26, 2000
    Assignee: AMIC Technology, Inc.
    Inventors: Kou-Su Chen, Shih-Chun Fu, Jui-Te Chan