Patents by Inventor Jui-Ting Li

Jui-Ting Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7323879
    Abstract: A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit includes a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 29, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hua Kuo, Jui-Ting Li
  • Patent number: 7246019
    Abstract: A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: July 17, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Hua Kuo, Jui-Ting Li, Yanan Mou, Jiunn-Fu Liu
  • Publication number: 20070027647
    Abstract: A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 1, 2007
    Inventors: Shu-Hua Kuo, Jui-Ting Li, Yanan Mou, Jiunn-Fu Liu
  • Publication number: 20060085714
    Abstract: A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit comprises a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 20, 2006
    Inventors: Shu-Hua Kuo, Jui-Ting Li