Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract: An output queue of a multi-plane network device includes a first processing circuit, a plurality of storage devices and a second processing circuit. The first processing circuit generates packet selection information based on an arrival sequence of a plurality of packets. The storage devices store a plurality of packet linked lists for the output queue. The second processing circuit dequeues a packet from the output queue by selecting a linked list entry from the packet linked lists according to the packet selection information.

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract: A switching fabric of a network device has a load dispatcher, a plurality of store units, a storage device, a plurality of fetch units, and a load assembler. Each of the store units is used to perform a write operation upon the storage device. Each of the fetch units is used to perform a read operation upon the storage device. The load dispatcher is used to dispatch ingress traffic to the store units, wherein a data rate between the load dispatcher and each of the store units is lower than a data rate of the ingress traffic. The load assembler is used to collect outputs of the fetch units to generate egress traffic, wherein a data rate between the load assembler and each of the fetch units is lower than a data rate of the egress traffic.

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract: The invention discloses a voltage regulating apparatus which includes: an output stage providing the apparatus with an output voltage and producing a partial voltage of the output voltage; an error amplifier coupled to the output stage and comparing the partial voltage with a reference to produce a first voltage; a PWM unit coupled to the error amplifier and comparing the first voltage with a voltage signal to produce second and third voltages; a selection unit coupled to the error amplifier and the PWM unit and outputting a fourth voltage equalling either the first or the second voltage; a first transistor coupled to the selection unit and receiving the fourth voltage and a DC voltage; and a second transistor coupled to the PWM unit, the first transistor, and a ground and receiving the third voltage; wherein a connection point of the first and second transistors is connected to the output stage.

Abstract: The invention discloses a voltage regulating apparatus which includes: an output stage providing the apparatus with an output voltage and producing a partial voltage of the output voltage; an error amplifier coupled to the output stage and comparing the partial voltage with a reference to produce a first voltage; a PWM unit coupled to the error amplifier and comparing the first voltage with a voltage signal to produce second and third voltages; a selection unit coupled to the error amplifier and the PWM unit and outputting a fourth voltage equalling either the first or the second voltage; a first transistor coupled to the selection unit and receiving the fourth voltage and a DC voltage; and a second transistor coupled to the PWM unit, the first transistor, and a ground and receiving the third voltage; wherein a connection point of the first and second transistors is connected to the output stage.

Abstract: A control circuit and method for managing multicast packets is implemented in a network switch to improve the efficiency of bandwidth utilization. The control circuit comprises an internal control buffer which is subdivided into multiple storage sections. Each storage section consists of buffer-control records including valid bit, counter value, control pointer, and tag number. When the tag number of a coming multicast packet indicates that the internal control buffer is full, the control data of the coming multicast packet will be copied to an external control memory. On the other hand, the control data of the coming multicast packet will be directly stored in the control buffer if otherwise. After each multicast packet transmission, the control data in the control buffer can be accessed and updated. Consequently, the traffic between the network switch and the external memories can be reduced to the minimum, thereby to improve the efficiency of the bandwidth utilization.