Abstract: A method includes receiving an integrated circuit (IC) design layout that includes a design boundary and a pair of design fin patterns having a fin spacing and a fin pitch. The method further includes creating a mandrel mask pattern, which includes determining an edge of the mandrel mask pattern based on a location of the design boundary, the fin spacing, and the fin pitch, and determining a width of the mandrel mask pattern based on the fin spacing and the fin pitch. The method further includes creating a cut mask pattern based on the mandrel mask pattern and the design fin patterns, wherein the cut mask pattern is configured to protect an area of a semiconductor wafer corresponding to the design fin patterns. The method further includes fabricating a mandrel mask having the mandrel mask pattern and fabricating a cut mask having the cut mask pattern.

Abstract: The present disclosure provides a method that includes receiving a circuit layout that includes circuit features and a mark pattern to be formed on a same material layer over an integrated circuit (IC) substrate, the circuit features being longitudinally oriented along a first direction and being distanced from each other along a second direction that is orthogonal to the first direction; fragmenting the mark pattern to generate a fragmented mark pattern having fragmented mark features such that the fragmented mark features are configured in parallel and are longitudinally oriented along a third direction; and generating a modified circuit layout for circuit fabrication, the modified circuit layout including the circuit features and the fragmented mark pattern.