Patents by Inventor Jui-Wen Yang
Jui-Wen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968817Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.Type: GrantFiled: February 28, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
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Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11764166Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.Type: GrantFiled: March 30, 2021Date of Patent: September 19, 2023Assignees: Industrial Technology Research Institute, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Wen Yang, Hsin-Cheng Lai, Chieh-Wei Feng, Tai-Jui Wang, Yu-Hua Chung, Tzu-Yang Ting
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Publication number: 20230071946Abstract: The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.Type: ApplicationFiled: March 30, 2022Publication date: March 9, 2023Applicant: Industrial Technology Research InstituteInventors: Chieh-Wei Feng, Tai-Jui Wang, Jui-Wen Yang, Tzu-Yang Ting
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Patent number: 11251115Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1?(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.Type: GrantFiled: January 8, 2021Date of Patent: February 15, 2022Assignee: Industrial Technology Research InstituteInventors: Shao-An Yan, Chieh-Wei Feng, Tzu-Yang Ting, Tzu-Hao Yu, Chien-Hsun Chu, Jui-Wen Yang, Hsin-Cheng Lai
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Publication number: 20220005768Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.Type: ApplicationFiled: March 30, 2021Publication date: January 6, 2022Applicant: Industrial Technology Research InstituteInventors: Jui-Wen Yang, Hsin-Cheng Lai, Chieh-Wei Feng, Tai-Jui Wang, Yu-Hua Chung, Tzu-Yang Ting
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Publication number: 20210197643Abstract: A temperature control method, including periodically sensing an air temperature of a space, and periodically sensing a surface temperature of each of a plurality of interior surfaces; in response to the air temperature and the surface temperatures being less than a target temperature, calculating an air heating duration of an air conditioner and a surface heating duration of each of a plurality of heater devices arranged in an array according to the target temperature, the air temperature and the surface temperatures; performing an air heating operation according to the air heating duration and performing surface heating operations according to the surface heating durations; and in response to the air temperature currently sensed and the surface temperatures currently sensed reaching the target temperature, instructing the air conditioner to stop performing the air heating operation.Type: ApplicationFiled: March 30, 2020Publication date: July 1, 2021Applicant: Industrial Technology Research InstituteInventors: Jui-Wen Yang, Yi-Cheng Lu, Min-Hsiung Liang, Tzu-Hao Yu, Tzu-Yang Ting
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Patent number: 10644167Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.Type: GrantFiled: March 6, 2018Date of Patent: May 5, 2020Assignees: Industrial Technology Research Institute, Intellectual Property Innovation CorporationInventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu
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Publication number: 20190140106Abstract: A thin film transistor including a flexible substrate, a semiconductor layer, a first gate, and a first gate dielectric layer is provided. The semiconductor layer is located on the flexible substrate. The first gate is located on the flexible substrate and corresponds to a portion of the semiconductor layer. The first gate dielectric layer is located between the first gate and the semiconductor layer. The first gate dielectric layer is in contact with the semiconductor layer, and the hydrogen atom concentration of the first gate dielectric layer is less than 6.5×1020 atoms/cm3. A method of manufacturing the thin film transistor is also provided.Type: ApplicationFiled: March 6, 2018Publication date: May 9, 2019Applicants: Industrial Technology Research Institute, Intellectual Property Innovation CorporationInventors: Tai-Jui Wang, Yung-Hui Yeh, Jui-Wen Yang, Hsiao-Chiang Yao, Chun-Hung Chu