Patents by Inventor Jui-Yao Lai
Jui-Yao Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210366779Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Inventors: Jui-Yao LAI, Ru-Gun LIU, Sai-Hooi YEONG, Yen-Ming CHEN, Yung-Sung YEN, Ying-Yan CHEN
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Patent number: 11177211Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: GrantFiled: March 6, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
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Patent number: 11088030Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.Type: GrantFiled: May 17, 2016Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Ru-Gun Liu, Sai-Hooi Yeong, Yen-Ming Chen, Yung-Sung Yen, Ying-Yan Chen
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Patent number: 10916475Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.Type: GrantFiled: November 30, 2018Date of Patent: February 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Ying-Yan Chen, Yen-Ming Chen, Sai-Hooi Yeong, Yung-Sung Yen, Ru-Gun Liu
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Publication number: 20200211957Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: ApplicationFiled: March 6, 2020Publication date: July 2, 2020Inventors: Kuo-Yen LIU, Boo YEH, Min-Chang LIANG, Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN, Yen-Ming CHEN
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Patent number: 10629527Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: GrantFiled: November 20, 2018Date of Patent: April 21, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
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Patent number: 10373963Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.Type: GrantFiled: May 22, 2018Date of Patent: August 6, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen, Ying-Yan Chen, Jeng-Ya David Yeh
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Patent number: 10269697Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: GrantFiled: March 4, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
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Publication number: 20190115261Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Inventors: Jui-Yao LAI, Ying-Yan CHEN, Yen-Ming CHEN, Sai-Hooi YEONG, Yung-Sung YEN, Ru-Gun LIU
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Publication number: 20190109087Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: ApplicationFiled: November 20, 2018Publication date: April 11, 2019Inventors: Kuo-Yen LIU, Boo YEH, Min-Chang LIANG, Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN, Yen-Ming CHEN
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Patent number: 10169515Abstract: A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.Type: GrantFiled: November 16, 2015Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kam-Tou Sio, Tsung-Yao Wen, Chih-Ming Lai, Hui-Ting Yang, Jui-Yao Lai, Chih-Liang Chen, Chun-Kuang Chen, Ru-Gun Liu, Yen-Ming Chen, Chew-Yuen Young
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Patent number: 10157826Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.Type: GrantFiled: March 4, 2016Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yen Liu, Boo Yeh, Min-Chang Liang, Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen, Yen-Ming Chen
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Patent number: 10157845Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.Type: GrantFiled: December 21, 2017Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen
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Patent number: 10083969Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.Type: GrantFiled: February 21, 2017Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ying-Yan Chen, Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen
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Patent number: 10084033Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.Type: GrantFiled: October 23, 2017Date of Patent: September 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Yao Lai, Chun-Yi Lee, Shyh-Wei Wang, Yen-Ming Chen
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Publication number: 20180269213Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Inventors: Jui-Yao LAI, Sai-Hooi YEONG, Yen-Ming CHEN, Ying-Yan CHEN, Jeng-Ya David YEH
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Patent number: 9997522Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.Type: GrantFiled: December 3, 2015Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen, Ying-Yan Chen, Jeng-Ya David Yeh
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Publication number: 20180122743Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.Type: ApplicationFiled: December 21, 2017Publication date: May 3, 2018Inventors: Jui-Yao LAI, Sai-Hooi YEONG, Ying-Yan CHEN
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Publication number: 20180061930Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.Type: ApplicationFiled: October 23, 2017Publication date: March 1, 2018Inventors: Jui-Yao LAI, Chun-Yi LEE, Shyh-Wei WANG, Yen-Ming CHEN
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Patent number: 9881872Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.Type: GrantFiled: January 15, 2016Date of Patent: January 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Yao Lai, Sai-Hooi Yeong, Ying-Yan Chen