Patents by Inventor Jui-Yao (Ray) Yang

Jui-Yao (Ray) Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120324180
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Application
    Filed: August 30, 2012
    Publication date: December 20, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao ("Ray") Yang, Siamack Nemazie
  • Publication number: 20120011335
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao (Ray) Yang, Siamack Nemazie
  • Patent number: 8055816
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: November 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao (Ray) Yang, Siamack Nemazie
  • Publication number: 20100262721
    Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
    Type: Application
    Filed: April 9, 2009
    Publication date: October 14, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao ("Ray") Yang, Siamack Nemazie
  • Publication number: 20100211834
    Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.
    Type: Application
    Filed: February 18, 2009
    Publication date: August 19, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao ("Ray") Yang