Patents by Inventor Jui-Yean Chiu

Jui-Yean Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107737
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Publication number: 20190252272
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 10276457
    Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Publication number: 20180286765
    Abstract: A method for measuring charge accumulation in a fabrication process of a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided. Subsequently, the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate. The first conductivity type is different from the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region. The inverter is electrically connected to the control transistor. Thereafter, a wafer acceptance test (WAT) is performed to evaluate the charge accumulation.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu