Patents by Inventor JUI-YEN LIN
JUI-YEN LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830818Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: GrantFiled: February 1, 2022Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11808834Abstract: A phased-array Doppler radar includes a two-way splitter, a transmit antenna, a receive antenna array, an ILO, a demodulation unit and a digital signal processing unit. A reference signal is split by the two-way splitter to the transmit antenna for transmission to targets and the ILO for injection locking. Signals reflected by the targets are received by the receive antenna array as received signals. An injection-locked signal generated by the ILO and the received signals received by the receive antenna array are delivered to the demodulation unit. The received signals are demodulated into baseband I/Q signals by the demodulation unit that uses the injection-locked signal as a local oscillator signal. The baseband I/Q signals are processed by the digital signal processing unit to obtain a digital beamforming pattern.Type: GrantFiled: November 23, 2020Date of Patent: November 7, 2023Assignee: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Tzyy-Sheng Horng, Chao-Kai Wen, Yi-Chen Lai, Yu-Chi Huang, Jui-Yen Lin, De-Ming Chian
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Patent number: 11737362Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.Type: GrantFiled: April 1, 2016Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11642033Abstract: A vital-sign radar sensor uses wireless internet signals to detect vital signs. It includes a first and second demodulation unit to demodulate an incident and reflected wireless internet signal with an injection-locked oscillator into a first and second demodulated signal, respectively. The combined use of the first and second demodulated signals can eliminate the influence of communication modulation on the extraction process of a Doppler shift due to vital signs. Moreover, the vital-sign radar sensor is a receive-only device so that it won't cause interference to ambient wireless communication networks.Type: GrantFiled: January 29, 2021Date of Patent: May 9, 2023Assignee: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Tzyy-Sheng Horng, Yi-Chen Lai, Jui-Yen Lin
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Publication number: 20230036595Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.Type: ApplicationFiled: February 8, 2020Publication date: February 2, 2023Inventors: Deepak THIMMEGOWDA, Brian J. CLEEREMAN, Srivardhan GOWDA, Jui-Yen LIN, Liu LIU, Krishna PARAT, Jong Sun SEL, Baosuo ZHOU
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Publication number: 20220192512Abstract: A vital-sign radar sensor uses wireless internet signals to detect vital signs. It includes a first and second demodulation unit to demodulate an incident and reflected wireless internet signal with an injection-locked oscillator into a first and second demodulated signal, respectively. The combined use of the first and second demodulated signals can eliminate the influence of communication modulation on the extraction process of a Doppler shift due to vital signs. Moreover, the vital-sign radar sensor is a receive-only device so that it won't cause interference to ambient wireless communication networks.Type: ApplicationFiled: January 29, 2021Publication date: June 23, 2022Inventors: Tzyy-Sheng Horng, Yi-Chen Lai, Jui-Yen Lin
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Publication number: 20220157729Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 11264329Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: GrantFiled: April 1, 2016Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Publication number: 20210356577Abstract: A phased-array Doppler radar includes a two-way splitter, a transmit antenna, a receive antenna array, an ILO, a demodulation unit and a digital signal processing unit. A reference signal is split by the two-way splitter to the transmit antenna for transmission to targets and the ILO for injection locking. Signals reflected by the targets are received by the receive antenna array as received signals. An injection-locked signal generated by the ILO and the received signals received by the receive antenna array are delivered to the demodulation unit. The received signals are demodulated into baseband I/Q signals by the demodulation unit that uses the injection-locked signal as a local oscillator signal. The baseband I/Q signals are processed by the digital signal processing unit to obtain a digital beamforming pattern.Type: ApplicationFiled: November 23, 2020Publication date: November 18, 2021Inventors: Tzyy-Sheng Horng, Chao-Kai Wen, Yi-Chen Lai, Yu-Chi Huang, Jui-Yen Lin, De-Ming Chian
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Patent number: 11063137Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.Type: GrantFiled: June 28, 2016Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Jui-Yen Lin, Chen-Guan Lee, Joodong Park, Walid M. Hafez, Kun-Huan Shih
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Publication number: 20210074642Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.Type: ApplicationFiled: April 1, 2016Publication date: March 11, 2021Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Patent number: 10923574Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: GrantFiled: September 13, 2019Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan
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Patent number: 10903372Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.Type: GrantFiled: December 11, 2015Date of Patent: January 26, 2021Assignee: Intel CorporationInventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan
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Publication number: 20200194599Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.Type: ApplicationFiled: December 11, 2015Publication date: June 18, 2020Inventors: Kinyip PHOA, Jui-Yen LIN, Nidhi NIDHI, Chia-Hong JAN
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Publication number: 20200006509Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Applicant: INTEL CORPORATIONInventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
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Patent number: 10505034Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.Type: GrantFiled: June 19, 2015Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Xiaodong Yang, Jui-Yen Lin, Kinyip Phoa, Nidhi Nidhi, Yi Wei Chen, Kun-Huan Shih, Walid M. Hafez, Curtis Tsai
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Patent number: 10431661Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: GrantFiled: December 23, 2015Date of Patent: October 1, 2019Assignee: INTEL CORPORATIONInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan
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Publication number: 20190123170Abstract: An embodiment includes an apparatus comprising: a transistor including a source, a drain, and a gate that has first and second sidewalls; a first spacer on the first sidewall between the drain and the gate; a second spacer on the second sidewall between the source and the gate; and a third spacer on the first spacer. Other embodiments are described herein.Type: ApplicationFiled: June 28, 2016Publication date: April 25, 2019Inventors: Jui-Yen Lin, Chen-Guan Lee, Joodong Park, Walid M. Hafez, Kun-Huan Shih
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Patent number: 10229866Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.Type: GrantFiled: June 22, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Yi Wei Chen, Kinyip Phoa, Nidhi Nidhi, Jui-Yen Lin, Kun-Huan Shih, Xiaodong Yang, Walid M. Hafez, Curtis Tsai
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Publication number: 20190051806Abstract: An apparatus includes a first semiconductor fin and a second semiconductor fin that is parallel to the first semiconductor fin. The first semiconductor fin extends from a first region of a substrate near a circuit that produces thermal energy when a circuit is in operation to a second region of the substrate, which is disposed away from the circuit. The second semiconductor fin extends from the first region to the second region and has a different material composition than the first semiconductor fin. The first and second semiconductor fins collectively exhibit a Seebeck effect when the circuit is in operation. The apparatus includes interconnects to couple the first and second semiconductor fins to a power supply circuit to transfer electricity generated due to the Seebeck effect to the power supply circuit.Type: ApplicationFiled: April 1, 2016Publication date: February 14, 2019Inventors: Kinyip Phoa, Jui-Yen Lin, Nidhi Nidhi, Chia-Hong Jan