Patents by Inventor Jui-Yu Wu

Jui-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200133018
    Abstract: A DOE module including a transparent substrate, a first electrode, a second electrode, a first sensing wire, a sensing layer, a DOE layer, and an insulating layer is provided. The first electrode is disposed on the transparent substrate, and the second electrode is disposed on the transparent substrate. The first sensing wire is distributed on the transparent substrate and electrically connected to the first electrode. The sensing layer is distributed on the transparent substrate and electrically connected to the second electrode. The first sensing wire is insulated from the sensing layer to form a capacitance between the first sensing wire and the sensing layer. The DOE layer is disposed on the transparent substrate. The insulating layer covers the first sensing wire and the sensing layer. The insulating layer has a first opening and a second opening respectively exposing the first electrode and the second electrode.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 30, 2020
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Biing-Seng Wu, Han-Yi Kuo, Kuan-Ming Chen, Chih-Yu Chuang, Shi-Jen Wu, Jui-Ni Li, Cheng-Hung Tsai, Chin-Yuan Chiang, Chia-Ming Hsu, Chiau-Ling Huang
  • Publication number: 20200123003
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Patent number: 10607794
    Abstract: A keyboard includes a plurality of key modules. Each key module includes a baseplate, a circuit membrane disposed on the baseplate, a metal dome disposed on the circuit membrane, an elastic member disposed on the metal dome, and a keycap. The elastic member and the linkage member are configured to be a movable switch mechanism. The circuit membrane has a conductive circuit. The metal dome has an opening corresponding to the conductive circuit of the circuit membrane. A trigger portion protrudes from an underside of the elastic member. When the keycap is pressed, the trigger portion passes through the opening of the metal dome, and moves downwards to abut against the conductive circuit to induce a conducting signal. The movable switch mechanism can be made by a double injection molding method.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 31, 2020
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lin Chen, Jui-Yu Wu
  • Patent number: 10532925
    Abstract: The present disclosure relates to a micro-electromechanical system (MEMs) package. In some embodiments, the MEMs package has a plurality of conductive interconnect layers disposed within a dielectric structure over an upper surface of a first substrate. A heating element is electrically coupled to a semiconductor device within the first substrate by one or more of the plurality of conductive interconnect layers. The heating element is vertically separated from the first substrate by the dielectric structure. A MEMs substrate is coupled to the first substrate and has a MEMs device. A hermetically sealed chamber surrounding the MEMs device is disposed between the first substrate and the MEMs substrate. An out-gassing material is disposed laterally between the hermetically sealed chamber and the heating element.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Chih-Yu Wang, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
  • Publication number: 20200006639
    Abstract: The present disclosure describes an exemplary method that can prevent or reduce out-diffusion of Cu from interconnect layers to magnetic tunnel junction (MTJ) structures. The method includes forming an interconnect layer over a substrate that includes an interlayer dielectric stack with openings therein; disposing a metal in the openings to form corresponding conductive structures; and selectively depositing a diffusion barrier layer on the metal. In the method, selectively depositing the diffusion barrier layer includes pre-treating the surface of the metal; disposing a precursor to selectively form a partially-decomposed precursor layer on the metal; and exposing the partially-decomposed precursor layer to a plasma to form the diffusion barrier layer. The method further includes forming an MTJ structure on the interconnect layer over the diffusion barrier layer, where the bottom electrode of the MTJ structure is aligned to the diffusion barrier layer.
    Type: Application
    Filed: December 5, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Tang WU, Jui-Hung HO, Chin-Szu LEE, Meng-Yu WU, Szu-Hua WU
  • Patent number: 10513432
    Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Chun Weng, Lavanya Sanagavarapu, Ching-Hsiang Hu, Wei-Ding Wu, Shyh-Wei Cheng, Ji-Hong Chiang, Hsin-Yu Chen, Hsi-Cheng Hsu
  • Patent number: 10468493
    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
  • Publication number: 20190305993
    Abstract: An Ethernet communication circuit includes: an Ethernet cable connector for communicating data with other devices through an Ethernet cable; an Ethernet transformer coupled with the Ethernet cable connector and arranged to operably process signals transmitted from the Ethernet cable connector; an Ethernet physical layer circuit coupled with the Ethernet transformer and arranged to operably conduct physical layer operations on the signals transmitted from the Ethernet transformer; and a plurality of coupling capacitors respectively arranged between a portion of signal pins of the Ethernet physical layer circuit and the Ethernet transformer.
    Type: Application
    Filed: April 1, 2019
    Publication date: October 3, 2019
    Applicant: Realtek Semiconductor Corp.
    Inventors: Jui-Yu WU, Ting-Fa YU, Cheng-Cheng YEN, Wen-Fu WANG
  • Publication number: 20190295849
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Publication number: 20190285926
    Abstract: A display panel has a display region and a non-display region. The display panel includes a first substrate; a second substrate disposed opposite to the first substrate; a display medium disposed between the first substrate and the second substrate; and an adhesion structure disposed between the first substrate and the second substrate and in the non-display region, wherein a width of the adhesion structure ranges from 5 ?m to 500 ?m.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 19, 2019
    Inventors: Jui-Chu LAI, Sheng-Nan FAN, Chiu-Lien YANG, Shih-Hsiung WU, Feng-Yu LIN, Kuo-Liang CHUANG, Shu-Lan CHEN
  • Publication number: 20190285928
    Abstract: A display panel includes a first substrate; a second substrate disposed opposite to the first substrate; a display medium disposed between the first substrate and the second substrate; and a first engaging structure including a first protruding portion and a first receiving portion. The first protruding portion is disposed on a first surface of the first substrate, and the first receiving portion is disposed on a second surface of the second substrate. The first receiving portion has a first opening to expose a portion of the second surface of the second substrate. At least a portion of the first protruding portion is disposed within the first opening of the first receiving portion. The first protruding portion and the portion of the second surface of the second substrate exposed from the first opening are spaced apart by a distance.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 19, 2019
    Inventors: Kuo-Liang CHUANG, Shu-Lan CHEN, Chiu-Lien YANG, Sheng-Nan FAN, Shih-Hsiung WU, Jui-Chu LAI, Feng-Yu LIN
  • Patent number: 10396196
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, a doped region, a device region, a first isolation structure, a second isolation structure and a terminal. The semiconductor layer is disposed over the substrate. The doped region is disposed in the semiconductor layer. The device region is disposed on the doped region and includes a source, a drain and a gate. The first isolation structure is disposed in the semiconductor layer and surrounds the doped region. The second isolation structure surrounds the first isolation structure and is spaced apart from the first isolation structure. The terminal is disposed between the first isolation structure and the second isolation structure, and is equipotential with the source.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 27, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jui-Chun Chang, Shih-Kai Wu, Cheng-Yu Wang, Li-Yang Hong, Chia-Ming Hsu
  • Patent number: 10388749
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
  • Patent number: 10366896
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 10344828
    Abstract: A dual-shaft push-moving varying speed device includes a drive unit; an input shaft, having at least an odd-numbered input gear and at least an even-numbered input gear is coupled with the drive unit; an output shaft, having an end thereof penetrate through the input shaft and the drive unit, and the another end thereof possesses an output gear; a transmission shaft, including at least an odd-numbered output gear, at least an even-numbered output gear, and a transmission gear where the odd-numbered output gear is meshed with the corresponding odd-numbered input gear while the even-numbered output gear is meshed with the corresponding even-numbered input gear, and the transmission gear is meshed with the output gear; and at least a push-moving fork, being furnished between the odd-numbered input gear and the even-numbered input gear, selectively pushes the odd-numbered input gear and the even-numbered input gear to move.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 9, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Meng-Ru Wu, Chia Tsao, Peng-Yu Chen, Jui-Tang Tseng, Cheng-Ping Yang
  • Publication number: 20190164700
    Abstract: A key module including a key cap, a bottom plate, and a scissors structure is provided. The scissors structure has a first supporting member and a second supporting member pivoted to the key cap and the bottom plate respectively. The first supporting member has a plurality of protruding shafts, the second supporting member has a plurality of axle holes, and the protruding shafts are movably pivoted to the axle holes respectively.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 30, 2019
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Chun-Lin Chen, Ko-Hsiang Lin, Jui-Yu Wu
  • Publication number: 20190018501
    Abstract: A key structure including a bottom plate, a pivoting structure, a cap, a thin-film circuit board and a dome structure is provided. The bottom plate has a limiting unit. The pivoting structure is slidably disposed on the bottom plate and includes a first pivoting member and a second pivoting member. The cap is disposed on the pivoting structure and connects the pivoting structure. The cap moves with respect to the bottom plate up and down through the rotation of the first pivoting member with respect to the second pivoting member. The thin-film circuit board is disposed on the bottom plate and includes a switch element. The dome structure is disposed against between the pivoting structure and the thin-film circuit board and includes a metal dome located above the switch element.
    Type: Application
    Filed: May 29, 2018
    Publication date: January 17, 2019
    Inventors: Chun-Lin CHEN, Jui-Yu WU
  • Publication number: 20180358193
    Abstract: A keyboard includes a plurality of key modules. Each key module includes a baseplate, a circuit membrane disposed on the baseplate, a metal dome disposed on the circuit membrane, an elastic member disposed on the metal dome, and a keycap. The elastic member and the linkage member are configured to be a movable switch mechanism. The circuit membrane has a conductive circuit. The metal dome has an opening corresponding to the conductive circuit of the circuit membrane. A trigger portion protrudes from an underside of the elastic member. When the keycap is pressed, the trigger portion passes through the opening of the metal dome, and moves downwards to abut against the conductive circuit to induce a conducting signal. The movable switch mechanism can be made by a double injection molding method.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 13, 2018
    Inventors: Chun-Lin Chen, JUI-YU WU
  • Publication number: 20120088696
    Abstract: A micro electrochemical multiplex Real-Time PCR platform which can be widely used to rapidly amplify, examine, and quantify target nucleotides in real-time, and can be used in sepsis diagnosis, rapid detection of animal/plant viral or bacterial infections, plant disease control, real-time environmental monitoring, food industry contamination prevention, and improvement of agricultural varieties.
    Type: Application
    Filed: June 20, 2011
    Publication date: April 12, 2012
    Inventors: Yi-Chiuen HU, Jui-Yu Wu, Jun-Sheng Wang, Tsung-Tao Huang, Chih-Sheng Yu
  • Publication number: 20100144763
    Abstract: The invention relates to the compounds isolated from Evodia rutaecarpa (Juss.), in that has been demonstrated to inhibit topoisomerase I. Evodiamine, an alkaloidal compound is reported the topoisomerase I inhibitory activity. The effect of evodiamine acts by stabilizing the covalent complex between topoisomerase I and DNA, which results in a blockade of DNA replication and transcription.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 10, 2010
    Applicant: TAIPEI MEDICAL UNIVERSITY
    Inventors: Chun-Mao Lin, Chwen-Ming Shih, Jui-Yu Wu