Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

Abstract: A coil component includes a body having one surface and the other surface, opposing each other, both lateral surfaces respectively connecting the one surface and the other surface and opposing each other, and both end surfaces respectively connecting the both lateral surfaces and opposing each other; a coil unit disposed in the body; a first external electrode and a second external electrode, respectively connected to the coil unit and disposed to be spaced apart from each other on the one surface of the body; and a first insulating layer covering the other surface of the body, the both lateral surfaces of the body, and the both end surfaces of the body.

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Abstract: A semiconductor package may include: a substrate; a seed layer on a first surface of the substrate; a pad on the seed layer and including a first metal layer and a second metal layer on the first metal layer; an insulating layer on the first surface and including a side surface in contact with the second metal layer; and a semiconductor chip above a second surface of the substrate. An interface between the side surface of the insulating layer and the second metal layer may be nonplanar.

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

Abstract: A semiconductor package including: a first redistribution structure; a semiconductor chip on the first redistribution structure; a pad insulation layer on a lower surface of the first redistribution structure; a conductive pad extending into a lower surface of the pad insulation layer and electrically connected to the first redistribution structure; and a plurality of alignment patterns on an edge of the pad insulation layer, each of the plurality of alignment patterns including a first portion extending into a lower surface of the pad insulation layer and a second portion extending away from the lower surface of the pad insulation layer.

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

Abstract: A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

Abstract: A semiconductor package, comprising a redistribution substrate including an insulating layer and a first redistribution pattern; and a semiconductor chip electrically connected to the redistribution substrate, wherein the first redistribution pattern comprises a first barrier layer; a second barrier layer on the first barrier layer; and a via structure on the second barrier layer, wherein the first barrier layer comprises a first conductive material and the second barrier layer comprises a second conductive material different from the first conductive material.

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

Abstract: A redistribution substrate includes first and second insulating layers; a wiring layer, and a metal layer. The wiring pattern includes a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer. The metal layer covers an upper surface of the wiring pattern. The second insulating layer is provided on the first insulating layer and covers the pad portion and the metal layer. The wiring pattern includes a first metal. The metal layer includes the first metal and a second metal. The metal layer includes a first portion vertically overlapping the pad portion, and a second portion surrounding the first portion, and a concentration of the first metal in the first portion of the metal layer is greater than a concentration of the first metal in the second portion of the metal layer.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.