Abstract: An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

Abstract: A semiconductor package includes a wiring structure that includes a first insulating layer and a first conductive pattern inside the first insulating layer, a first semiconductor chip disposed on the wiring structure, an interposer that includes a second insulating layer, a second conductive pattern inside the second insulating layer, and a recess that includes a first sidewall formed on a first surface of the interposer that faces the first semiconductor chip and a first bottom surface connected with the first sidewall, where the recess exposes at least a portion of the second insulating layer, a first element bonded to the interposer and that faces the first semiconductor chip inside the recess, and a mold layer that covers the first semiconductor chip and the first element.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

Abstract: A redistribution substrate includes first and second insulating layers; a wiring layer, and a metal layer. The wiring pattern includes a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer. The metal layer covers an upper surface of the wiring pattern. The second insulating layer is provided on the first insulating layer and covers the pad portion and the metal layer. The wiring pattern includes a first metal. The metal layer includes the first metal and a second metal. The metal layer includes a first portion vertically overlapping the pad portion, and a second portion surrounding the first portion, and a concentration of the first metal in the first portion of the metal layer is greater than a concentration of the first metal in the second portion of the metal layer.

Abstract: A semiconductor device including a substrate and first and second packages thereon, the first package includes a first lower redistribution layer; a first core semiconductor stack thereon and including a first core chip and a first through via stacked on the first lower redistribution layer; and a first memory semiconductor stack on the first lower redistribution layer and including first memory chips stacked on the first lower redistribution layer, the second package includes a second lower redistribution layer; a second core semiconductor stack thereon and including a second core chip on the second lower redistribution layer; and a second memory semiconductor stack on the second lower redistribution layer and including second memory chips stacked on the second lower redistribution layer, the first through via penetrates the first core semiconductor stack, and the first and second lower redistribution layers are electrically connected to each other through the first through via.

Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

Abstract: Provided is a semiconductor package including a chip stack that includes first and second semiconductor chips stacked in a first direction and offset in a second direction intersecting the first direction, each of the first and second semiconductor chips comprising chip pads in the second direction, a redistribution substrate on the chip stack, first bonding wires connecting the redistribution substrate and the chip pads of the first semiconductor chip, and first vertical wires connecting the redistribution substrate and the chip pads of the second semiconductor chip. Each of the first bonding wires includes a first portion in contact with one of the chip pads of the first semiconductor chip and having a first width, and a second portion extending perpendicularly on the first portion and having a second width, each of the first vertical wires has a third width, and each of the second and third widths is smaller than the first width.

Abstract: A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.

Abstract: A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers has first extensions that outwardly protrude from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layer is from the substrate, the shorter length the first extension protrudes from the first lateral surface of the first semiconductor chip.

Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Abstract: A semiconductor device includes a first redistribution substrate, a semiconductor chip on a top surface of the first redistribution substrate, a conductive structure on the top surface of the first redistribution substrate and laterally spaced apart from the semiconductor chip, and a molding layer on the first redistribution substrate and covering a sidewall of the semiconductor chip and a sidewall of the conductive structure. The conductive structure includes a first conductive structure having a first sidewall, and a second conductive structure on a top surface of the first conductive structure and having a second sidewall. The first conductive structure has an undercut at a lower portion of the first sidewall. The second conductive structure has a protrusion at a lower portion of the second sidewall.

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

Abstract: A semiconductor package includes a lower package substrate including a lower redistribution insulation layer and a lower redistribution pattern; a semiconductor chip disposed on the lower package substrate; a molding member disposed on the lower package substrate and covering at least a portion of the semiconductor chip; a conductive post disposed in the molding member; and a lower redistribution pad disposed between the conductive post and the lower redistribution pattern, wherein the lower redistribution pad includes a pad hole extending from an upper surface of the lower redistribution pad toward a lower surface of the lower redistribution pad, and a portion of the conductive post is disposed in the pad hole.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate that includes a plurality of vias, a first chip stack on the substrate and including a plurality of first semiconductor chips that are sequentially stacked on the substrate, and a plurality of first non-conductive layers between the substrate and the first chip stack and between neighboring first semiconductor chips. Each of the first non-conductive layers includes first extensions that protrude outwardly from first lateral surfaces of the first semiconductor chips. The more remote the first non-conductive layers are from the substrate, the first extensions protrude a shorter length from the first lateral surfaces of the first semiconductor chips.

Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.