Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.

Abstract: A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes.

Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.

Abstract: A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes.

Abstract: In one aspect, a direct connected silicon control rectifier (DCSCR) includes a substrate having a semiconductor surface, a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor formed in the semiconductor surface. The parasitic PNP bipolar transistor includes a p+ emitter, an nbase and a pcollector and the parasitic NPN bipolar includes an n+ emitter, a pbase and an ncollector. The DCSCR also includes an electrically conductive line connecting an n+ contact to the nbase to a p+ contact to the pbase so that the nbase and the pbase are shorted.

Abstract: In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

Abstract: An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer.

Abstract: In one aspect, a direct connected silicon control rectifier (DCSCR) includes a substrate having a semiconductor surface, a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor formed in the semiconductor surface. The parasitic PNP bipolar transistor includes a p+ emitter, an nbase and a pcollector and the parasitic NPN bipolar includes an n+ emitter, a pbase and an ncollector. The DCSCR also includes an electrically conductive line connecting an n+ contact to the nbase to a p+ contact to the pbase so that the nbase and the pbase are shorted.

Abstract: An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer.