Abstract: A frequency modulated output of a Digital Locked Loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.

Abstract: A frequency modulated output of a digital locked loop (DLL) is implemented with a Johnson Counter outputting a sample clock and a synchronized digital code at a multiple of the sample clock. The digital code drives a digital-to-analog converter to generate a frequency modulated control signal. The control signal is summed with the center frequency control from the digital locked loop digital filter to provide a frequency modulated center frequency control signal to the DLL oscillator.

Abstract: An integrated circuit (10) includes a measurement circuit (20) for determining if a transistor (26) has normal gate leakage current or has a gate leakage current which is greater than normal. A transistor such as transistor (26) may be in a condition known as quasi-breakdown which typically occurs in response to some electrical stress. The characteristic of quasi-breakdown is that there is a very significant increase in gate leakage current, the transistor continues to function as a transistor but perhaps with degraded performance, and the transistor will fail if it continues to receive the stresses that caused it to go into quasi-breakdown. Thus, the measurement circuit (20), which is included on the integrated circuit (10), provides an early warning that a transistor, a device under test (26), is going to fail if the operating conditions remain the same.

Abstract: A data processing system (20) includes a plurality of modules (44, 48) and an analog-to-digital converter (ADC) (46). The ADC (46) includes at least one port terminal (66) for transmitting test information from the ADC (46). The plurality of modules (44,48) and the ADC (46) are coupled to a central processing unit (CPU) (22) via an intermodule bus (42). A tester can exchange test information with the ADC (46) directly through the port terminal (66) instead of using the intermodule bus (42). Also, various sub-modules (62, 64, 60, 74) of the ADC (46) can be independently tested without performing a conversion process.

Abstract: An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.

Abstract: A current mode transmitter (21) receives an input signal and converts the input signal to a current having at least two values. The current is transmitted across a transmission line (27) to a current mode receiver (30). The current mode receiver (30) has a low impedance input node (102) coupled to the transmission line (27) for receiving the current. Complementary voltage-follower transistors (35, 36) in the receiver (30) are connected to the transmission line (27). A current mirror (31, 42) is coupled to each of the voltage-follower transistors (35, 36) to convert the current to a CMOS signal. The reduced signal swing of the transmitted signal reduces RFI emissions as compared to a signal having a larger signal swing.

Abstract: A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Abstract: A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Abstract: An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), has a Pause bit which can be used to create multiple sub-queues of A/D conversions without requiring the use of interrupts. The Pause bit can be used to place a queue in a pause state. When a queue enters a pause state, the scanning of CCWs (82) is stopped. The queue must then receive a trigger in order for the scanning of CCWs (82) to continue again.

Abstract: An analog-to-digital conversion system and method provide selectable data formats for each converted digital result value. Each digital result is stored in a register or table word. Information from a host processor is used to select a desired data format. In one embodiment the address range used to read the digital result serves to select the appropriate data format option, which may be, for example, left-justified or right-justified data, and signed or unsigned data. In another embodiment, one or more command words from the processor are used to select the desired data format.

Abstract: A sampling circuit (10, 10') selectively samples, stores and provides multiple output signals with a single amplifier (30). A sampling capacitor (20, 28) is used for each input channel. In order to minimize crosstalk between the multiple channels, each sampling capacitor is selectively electrically isolated from an input of the single amplifier by a switch (18, 25). Each sampling capacitor is further selectively electrically isolated from an output of the single amplifier by another switch (19, 26). A switch structure (50, 52, 54) which is guard ring protected may be used at the input of each channel to further minimize crosstalk errors.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a resistor digital to analog converter (32). In one form, the analog to digital converter uses a small amount of resistor test logic (44) to test for defects in the resistor array (42), the switch array (38), and the optional decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry, which includes some analog circuitry, is tested by using a pull-up function and a pull-down function that can be overdriven by properly functioning circuitry. As a result of using resistor test logic (44), a very quick pass/fail functional test using digital logic levels as inputs can be performed on the analog to digital converter (14). The quick functional test does not require analog inputs or time-consuming analog to digital conversions.

Abstract: A method and apparatus for testing an analog to digital converter (14) having a capacitor digital to analog converter (30). In one form, the analog to digital converter uses a small amount of capacitor test logic (44) to test for opens and shorts in the capacitor array (42), the switch logic (38), and the decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by using AND and OR logical functions. As a result of using capacitor test logic (44), a very quick pass/fail functional test can be performed on the analog to digital converter (14) without requiring the analog to digital converter (14) to perform time-consuming analog to digital conversions.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers.

Abstract: An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or memory table. The command word or words may specify the conversion time per analog input channel or group of channels, and per conversion or conversion sequence. In one embodiment a control table comprises a plurality of conversion command words (CCW's). Each CCW designates conversion parameters including the input sample time.

Abstract: A power-on-reset circuit which functions with variations in process, temperature and supply voltage is provided. A differential comparator structure is provided which utilizes a differential pair of transistors and which has a substantially constant intrinsic offset voltage associated therewith. The intrinsic offset voltage is created by making one of the transistors of the differential pair of lightly doped depletion device and the other transistor a heavily doped depletion device. A second reference voltage is provided in response to a detected power-up voltage and is implemented with a voltage divider. Power-on-reset is provided in response to the relationship of the levels of the first and second reference voltages.

Abstract: An I/O circuit is provided having a terminal for either receiving an input signal or providing an output signal. In one form, the circuit may be utilized in a system with multiple I/O circuits coupled via a two-wire interconnection having a common ground conductor throughout the system. Input signal levels are sensed within a narrow voltage range referenced, in part, to the V.sub.be of a bipolar transistor and independent of the power supply voltage of other interconnected circuits. In response to an enable signal, a differential amplifier provides an output drive signal proportional to the difference between the signal at the terminal and a reference voltage. The output drive signal is coupled to a driver stage which provides a predetermined limited current at the terminal, thereby providing an output signal. A voltage limiter allows the circuit to use bipolar transistors in a P-well CMOS process and to receive input voltages greater than the supply voltage of the circuit.

Abstract: A code conversion circuit comprising logic for converting an n-bit binary number having a sign bit in two's complement code to sign-magnitude code is provided where n is an integer. The logic identifies whether or not the binary number is positive or negative. Regardless of polarity, the sign bit and least significant bit are directly outputted. If the binary number is positive, all bits are outputted with unchanged logic states. If the binary number is negative, the least significant bit of the n magnitude bits which has a logic one value is identified. The remaining n magnitude bits of higher significance are inverted and outputted with the other magnitude bits.

Abstract: A digital to analog converter which provides positive and negative analog output signals in response to a digital input number is disclosed. The input number has n bits including a sign bit and n-1 magnitude bits, where n is an integer. An input receives the n-1 magnitude bits and is coupled to switches for selectively coupling a predetermined reference voltage to a capacitance portion comprising a rank ordered plurality of capacitors. First and second charges related to first and second portions of said n-1 magnitude bits, respectively, are sequentially integrated with respect to time by an integrator which is selectively coupled to the capacitance portion to provide an analog output signal. A buffer output amplifier selectively samples and holds the analog output signal.