Patents by Inventor Jules D. Levine

Jules D. Levine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6153969
    Abstract: A field emission display device includes groupings of microtip emitters 14 which are energized by applying a negative potential to cathode 16 relative to the signal electrode 22, thereby inducing an electric field which draws streams of electrons 38 from the apexes of microtips 14. Electrons 38 emitted from microtips 14 impinge upon extraction plate 36 causing emission of a secondary stream of electrons 40 which are accelerated toward anode 40. Apparatus and methods for controlling these primary and secondary electron streams are described.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: November 28, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Jules D. Levine
  • Patent number: 5911616
    Abstract: A computer image display device includes a light transparent glass anode plate (10) spaced from a cathode substrate (12) which has a plurality of microtips (14). Plate (10) has an inside surface (25) which is contoured with an array of prisms (36) having equal sides (58, 59) that converge rearwardly toward apexes (38) of peaks (36). Apexes (38) are covered with light absorbing material (47), then covered at anode comb forming regions (51, 52, 53) with conductive material (48). Different color luminescing phosphors (24a, 24b, 24c) are applied over the respective anode combs (51, 52, 53). Sides (58, 59) direct ambient light toward apexes (38) for absorption by material (47). Light emitted by phosphors (24a, 24b, 24c) is directed by valleys (60) toward outside surface (35) of plate (10).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 15, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Chi-Cheong Shen, Bruce E. Gnade
  • Patent number: 5902165
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by an insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays of microtips (14) are located in mesh spacings (16), within apertures (26) formed in extraction electrode (22) and subcavities (141) formed through apertures (26) in insulating spacer (125). Subcavities (141a) are open to row-adjacent and column-adjacent subcavities (141b, 141c) to form larger main cavities (144). Posts (143) of insulating spacer (125) separate diagonally-adjacent cavities (141d). Subcavities (141) are formed by over-etching a layer of insulating spacer material (25) through apertures (26) before or after forming microtips (14) through the same apertures (26). Over-etching reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: May 11, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Kenneth G. Vickers
  • Patent number: 5871383
    Abstract: A grooved anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B. In one embodiment, grooves 50, having generally straight sidewalls, are formed in the upper surface of planar substrate 42 at the interstices of conductors 46. In a second embodiment, grooves 50', which provide a substantial undercutting of the material of substrate 42' adjacent the edges of conductors 46', are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. A substantially opaque, electrically insulating material 52 is affixed to substrate 42 in the grooves 50 formed between conductors 46, acting as a barrier to the passage of ambient light into and out of the device.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 16, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Chi-Cheong Shen, Bruce E. Gnade
  • Patent number: 5836799
    Abstract: A method of fabricating electron emission structures 28 having enhanced emission characteristics. The method comprises the steps of providing a substrate 10 having electron emission structures 5 thereon and having a layer 5" over the electron emission structures. The layer 5" having apertures 30 in alignment with said electron emission structures 5. Then modifying the electron emission structures 5 through the apertures 30 with a directional ion milling beam; thereby creating modified electron emission structures 17,29 with enhanced emission efficiency.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: November 17, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Kenneth G. Vickers
  • Patent number: 5759078
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by an insulating layer (125) from a cathode electrode including a conductive mesh (18). Hexagonal close-packed arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in extraction electrode (22). Microtips (14) are formed on a conductive plate (17) laterally spaced from mesh structure (18) by a resistive layer (15). Insulating layer (125) is etched to connect apertures (26) and place microtips (14) in a common cavity within each mesh spacing (16).
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: June 2, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Kenneth G. Vickers, Robert H. Taylor
  • Patent number: 5711694
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). Apertures (26) are arranged in regular, periodic arrays (23, 23', 123, 123') defining lattices having occupied apertured positions and internal unapertured vacancy positions (150, 150'). The insulating spacer (125) is etched to undercut electrode (22) to connect apertured lattice positions, forming a common cavity (141) for microtips (14) within each mesh spacing (16), and leaving central posts (143) at the unapertured vacancies (150, 150'). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: January 27, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Chi-Cheong Shen, Robert Taylor
  • Patent number: 5643033
    Abstract: An anode plate 50 for use in a field emission flat panel display device comprises a transparent planar substrate 58 having a plurality of electrically conductive, parallel stripes 52 comprising the anode electrode of the device, which are covered by phosphors 54.sub.R, 54.sub.G and 54.sub.B. A substantially opaque, electrically insulating material 56 is affixed to substrate 58 in the spaces between conductors 52, acting as a barrier to the passage of ambient light into and out of the device. The electrical insulating quality of opaque material 56 increases the electrical isolation of conductive stripes 52 from one another, reducing the risk of breakdown due to increased leakage current. Opaque material 56 preferably comprises glass having impurities dispersed therein, wherein the impurities may include one or more organic dyes, selected to provide relatively uniform opacity over the visible range of the electromagnetic spectrum.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce E. Gnade, Daron G. Evans, Scott R. Summerfelt, Jules D. Levine
  • Patent number: 5639356
    Abstract: To prevent degradation of field emission in a field emission device (FED) (10) resulting from the accumulation of contaminating impurities on the surface (42) of the microtips (26) of the FED (10), a high voltage pulse is applied at a cathode voltage control (46) connected between a grid conductor layer (24) and a metal mesh (18) of the FED (10). Upon application of the pulse, the impurities are desorbed from the surface (42) of the microtips (26) and are captured by a getter (44), which binds the impurities to its surface.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: June 17, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Jules D. Levine
  • Patent number: 5637958
    Abstract: A face plate (10) of an FED image display has a grooved rear surface (25) formed with projections (36). Projections (36) have surfaces (39) covered in regions (58, 59) with electrical conductive material (54) and different color emitting phosphor particles (56a, 56b). The regions (58, 59) define different color anode combs. Surfaces (39) in regions (61) between regions (58,59) are covered with insulative, light absorbing material (62) for absorption of ambient light. Surfaces (39) are formed to encourage forward direction of phosphor-emitted light. In one embodiment, surfaces (39) serve to channel ambient light rearwardly toward projection apexes (40) which are covered with light absorbing material (62). Projections (36) may be parallel elongated prisms, pyramids or cones.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: June 10, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Jules D. Levine
  • Patent number: 5621272
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by an insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays of microtips (14) are located in mesh spacings (16), within apertures (26) formed in extraction electrode (22) and subcavities (141) formed through apertures (26) in insulating spacer (125). Subcavities (141a) are open to row-adjacent and column-adjacent subcavities (141b, 141c) to form larger main cavities (144). Posts (143) of insulating spacer (125) separate diagonally-adjacent cavities (141d). Subcavities (141) are formed by over-etching a layer of insulating spacer material (25) through apertures (26) before or after forming microtips (14) through the same apertures (26). Over-etching reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: April 15, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Kenneth G. Vickers
  • Patent number: 5608286
    Abstract: A computer image display device includes a light transparent glass anode plate (10) spaced from a cathode substrate (12) which has a plurality of microtips (14). Plate (10) has an inside surface (25) which is contoured with an array of prisms (36) having equal sides (58, 59) that converge rearwardly toward apexes (38) of peaks (36). Apexes (38) are covered with light absorbing material (47), then covered at anode comb forming regions (51, 52, 53) with conductive material (48). Different color luminescing phosphors (24a, 24b, 24c) are applied over the respective anode combs (51, 52, 53). Sides (58, 59) direct ambient light toward apexes (38) for absorption by material (47). Light emitted by phosphors (24a, 24b, 24c) is directed by valleys (60) toward outside surface (35) of plate (10).
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: March 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Chi-Cheong Shen, Bruce E. Gnade
  • Patent number: 5608285
    Abstract: An mode plate 80 for use in a field emission flat panel display device comprises a transparent planar substrate 88 having a plurality of electrically conductive, parallel stripes 50 comprising the anode electrode of the device, which are covered by phosphors 84.sub.R, 84.sub.G and 84.sub.B. The conductors 50 which are covered by the same color phosphors are electrically interconnected by buses 52, 54, and 56. A substantially opaque, electrically insulating material 86 is affixed to substrate 88 in the spaces between conductors 50, acting as a barrier to the passage of ambient light into and out of the device. In addition, the same substantially opaque, electrically insulating material 86 is formed between the conductors 50 and the buses 52, 54, and 56, thereby providing electrical isolation between the two layers.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: March 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth G. Vickers, Chi-Cheong Shen, Bruce E. Gnade, Jules D. Levine
  • Patent number: 5606225
    Abstract: An anode plate 40, suitable for use in a field emission display tetrode, includes a transparent planar substrate 42 having thereon a layer 46 of a transparent, electrically conductive material, which comprises the anode electrode of the display tetrode. Barrier structures 48 comprising an electrically insulating, preferably opaque material, are formed on anode electrode 46 as a series of parallel ridges. Atop each barrier structure 48 are a series of electrically conductive stripes 50, which function as deflection electrodes. Luminescent material 52 overlies anode electrode 46 in the channels between barrier structures 48. Conductive stripes 50 are formed into three series such that every third stripe 50 is electrically interconnected. Deflection voltage controller 70 permits selective deflection of electrons toward the proper luminescent material 52.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: February 25, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Bruce E. Gnade
  • Patent number: 5589728
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by a dielectric insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays (12) of microtips (14) are located in mesh spacings (16), within apertures (26) formed in clusters (23) in extraction electrode (22). Microtips (14) are deposited through the apertures (26). Apertures (26) are arranged in regular, periodic arrays (23, 23', 123, 123') defining lattices having occupied apertured positions and internal unapertured vacancy positions (150, 150'). The insulating spacer (125) is etched to undercut electrode (22) to connect apertured lattice positions, forming a common cavity (141) for microtips (14) within each mesh spacing (16), and leaving central posts (143) at the unapertured vacancies (150, 150'). The etch-out reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: December 31, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Chi-Cheong Shen, Robert Taylor
  • Patent number: 5577943
    Abstract: A method of fabricating an anode plate 80 for use in a field emission device. The method comprises the steps of providing a substantially transparent substrate 88 having spaced-apart, electrically conductive regions 50 on a surface thereof, then coating the anode plate with a substantially opaque material 86. The opaque material 86 is removed from the surface of the conductive regions 50 in the active area 58, and from selected areas 60 of the interconnect portion of the conductive regions 50. A first bus 52 is provided for electrically connecting a first series 50.sub.R of the conductive regions 50, a second bus 54 is provided for electrically connecting a second series 50.sub.G of the conductive regions 50, and a third bus 56 is provided for electrically connecting a third series 50.sub.B of the conductive regions 50. Luminescent material of a first color 84.sub.R is applied to the first series of conductive regions 50.sub.R, luminescent material of a second color 84.sub.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: November 26, 1996
    Assignee: Texas Instruments Inc.
    Inventors: Kenneth G. Vickers, Chi-Cheong Shen, Bruce E. Gnade, Jules D. Levine
  • Patent number: 5569058
    Abstract: A porous dielectric material such as silica-based aerogel is used as the dielectric layer 48 between the gate and the cathode on the emitter plate 12 of a field emission device. Aerogel, which can have a relative dielectric constant as low as 1.03, is deposited over the resistive layer 44 of the emitter plate 12. Metal layer 49, functioning as the gate electrode, is subsequently deposited over the aerogel layer 48. The use of aerogel as a gate dielectric reduces power consumption. In a disclosed embodiment, aerogel layer 48 is comprised of sublayers 48a, 48b, and 48c of aerogels of differing densities, thereby providing better adhesion of the aerogel gate dielectric to both the resistive layer 44 and metal layer 49. Methods of fabricating the aerogel gate dielectric are disclosed.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 29, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Bruce Gnade, Chih-Chen Cho, Jules D. Levine
  • Patent number: 5569975
    Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: October 29, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Taylor, Jules D. Levine
  • Patent number: 5562517
    Abstract: A spacer 40 for use in a field emission device comprises a comb-like structure having a plurality of elongated filaments 42 joined to a support member 44. The filaments 42, which may be glass, are positioned longitudinally in a single layer between the facing surfaces of the anode structure 10 and the electron emitting structure 12. Support member 44 is positioned entirely outside the active regions of anode structure 10 and emitting structure 12. Spacer 40 provides voltage isolation between the anode structure 10 and the cathode structure 12, and also provides standoff of the mechanical forces of vacuum within the assembly. In a second embodiment, spacer 50 comprises elongated filaments 52 joined at each end to a support member 54a and 54b, the additional support facilitating handling, fabrication and assembly.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 8, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Taylor, Jules D. Levine
  • Patent number: 5541466
    Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: July 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Taylor, Jules D. Levine