Abstract: A core memory utilizes an auxiliary core that is driven concurrently with selected data cores to increase tolerances by automatically tracking the peaking time and the output magnitude. Wide variations in both the magnitude and duration of core output switching signals are compensated by use of the auxiliary core to control the sensing strobe time during a read part cycle and drive current duration during both read and write part cycles. Subtracting half of the auxiliary core output switching signal from a selected data core output switching signal normalizes the difference about zero volts with a one being indicated by the presence of a positive voltage and a zero by a negative voltage. With the reference threshold at zero there is no precise adjustment. Since the peak of the auxiliary core output tracks the peak of the selected data core output, substantial changes in the peaking and switching times do not interfere with accurate determinations of data core data states.