Patents by Inventor Julia Aksenton
Julia Aksenton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7642629Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: GrantFiled: August 13, 2007Date of Patent: January 5, 2010Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Patent number: 7495341Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: GrantFiled: January 30, 2007Date of Patent: February 24, 2009Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Patent number: 7479398Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: GrantFiled: August 21, 2007Date of Patent: January 20, 2009Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Publication number: 20080017879Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: ApplicationFiled: August 21, 2007Publication date: January 24, 2008Applicant: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Publication number: 20080012115Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: ApplicationFiled: August 13, 2007Publication date: January 17, 2008Applicant: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Patent number: 7265440Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: GrantFiled: May 10, 2005Date of Patent: September 4, 2007Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Publication number: 20070138498Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: ApplicationFiled: January 30, 2007Publication date: June 21, 2007Applicant: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Patent number: 7192796Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: GrantFiled: July 2, 2004Date of Patent: March 20, 2007Assignee: Tessera Technologies Hungary Kft.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Patent number: 6972480Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: GrantFiled: June 16, 2003Date of Patent: December 6, 2005Assignee: Shellcase Ltd.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Publication number: 20050205977Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: ApplicationFiled: May 10, 2005Publication date: September 22, 2005Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Publication number: 20050104179Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: ApplicationFiled: July 2, 2004Publication date: May 19, 2005Applicant: SHELLCASE LTD.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Publication number: 20040251525Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: SHELLCASE LTD.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian