Patents by Inventor Julia Chiu
Julia Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240319437Abstract: A photonic integrated circuit (PIC), a semiconductor assembly including the PIC, a multi-chip package including the PIC, and a method of forming the PIC. The PIC includes a PIC substrate, and a semiconductor layer on a top surface of the PIC substrate and including a semiconductor material and an optical component. The PIC substrate defines an air cavity therein extending in a direction from a bottom surface of the PIC substrate toward and in registration with the optical component. The semiconductor layer is free of any opening therethrough in communication with the air cavity.Type: ApplicationFiled: March 24, 2023Publication date: September 26, 2024Applicant: Intel CorporationInventors: Xiaoqian Li, Omkar G. Karhade, Nitin A. Deshpande, Julia Chiu, Chia-Pin Chiu, Kaveh Hosseini, Madhubanti Chatterjee
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Publication number: 20240006358Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Zhihua Zou, Omkar Karhade, Botao Zhang, Julia Chiu, Vivek Chidambaram, Yi Shi, Mohit Bhatia, Mostafa Aghazadeh
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Patent number: 10020375Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: October 6, 2017Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20180047825Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: October 6, 2017Publication date: February 15, 2018Applicant: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9812546Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: January 9, 2017Date of Patent: November 7, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9637810Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 21, 2015Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20170117378Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: January 9, 2017Publication date: April 27, 2017Applicant: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9580776Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 21, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20160035725Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: September 21, 2015Publication date: February 4, 2016Applicant: INTEL CORPORATIONInventors: Sameer S. Pradhan, DANIEL B. BERGSTROM, JIN-SUNG CHUN, JULIA CHIU
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Publication number: 20160035724Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: September 21, 2015Publication date: February 4, 2016Applicant: INTEL CORPORATIONInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Patent number: 9177867Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: GrantFiled: September 30, 2011Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Sameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Publication number: 20150041926Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.Type: ApplicationFiled: September 30, 2011Publication date: February 12, 2015Inventors: Sameer S. Pradhan, Daniel B. Bergstrom, Julia Chiu