Abstract: A system includes a library of elements to create a model describing a waveform parameter technique. A constraint checker verifies that the created model is correct by construction by needing no verification after compilation. The constraint checker also implements a valid programmable device build according to the waveform parameter technique. A placement decision module receives the verified models produces a placement decision for placing the waveform parameter technique based on the verified model in a programmable device. A synthesis tool receives the verified model from the placement decision module and synthesizes the waveform parameter technique based on the verified model. A link/loader receives the placement decision from the placement decision module and receives the synthesized technique from the synthesis tool. The link/loader also places the waveform parameter technique in the programmable device according to the placement decision.

Abstract: Embodiments of a system and method for runtime creation, assignment, deployment and updating of arbitrary radio waveform techniques for a radio waveform generation device are generally described herein. In some embodiments, a parser is arranged to parse packet data files to generate channel properties associated with at least one of a plurality of techniques. A user application may be coupled to the parser and arranged to process the channel properties into channelized waveform data according to the at least one of the plurality of techniques. A packetizer may be coupled to the user application and arranged to packetize the channelized waveform data. A digital-to-analog converter may be arranged to convert the channelized waveform data to analog RE signals representing the waveform corresponding to the at least one of the plurality of techniques.

Abstract: Embodiments of a system and method for providing efficient wideband inverse channelization for direct digital synthesizer based jamming techniques are generally described herein. In some embodiments, metadata associated with a technique for generating a waveform, such as frequency, phase and amplitude parameters, is received. Data select signals and data input are generated based on the received metadata. In-phase and quadrature signals are produced at an output of a first de-multiplexer and a second de-multiplexer, respectively, based on the data select signals and the data input. Frequency modulated signals generated by direct digital synthesizers may be combined in a channel using a separate, distinct channel combiner.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: Embodiments of a system and method for runtime creation, assignment, deployment and updating of arbitrary radio waveform techniques for a radio waveform generation device are generally described herein. In some embodiments, a parser is arranged to parse packet data files to generate channel properties associated with at least one of a plurality of techniques. A user application may be coupled to the parser and arranged to process the channel properties into channelized waveform data according to the at least one of the plurality of techniques. A packetizer may be coupled to the user application and arranged to packetize the channelized waveform data. A digital-to-analog converter may be arranged to convert the channelized waveform data to analog RF signals representing the waveform corresponding to the at least one of the plurality of techniques.

Abstract: Embodiments of a system and method for runtime creation, assignment, deployment and updating of arbitrary radio waveform techniques for a radio waveform generation device are generally described herein. In some embodiments, a parser is arranged to parse packet data files to generate channel properties associated with at least one of a plurality of techniques. A user application may be coupled to the parser and arranged to process the channel properties into channelized waveform data according to the at least one of the plurality of techniques. A packetizer may be coupled to the user application and arranged to packetize the channelized waveform data. A digital-to-analog converter may be arranged to convert the channelized waveform data to analog RF signals representing the waveform corresponding to the at least one of the plurality of techniques.

Abstract: Embodiments of a system and method for providing efficient wideband inverse channelization for direct digital synthesizer based jamming techniques are generally described herein. In some embodiments, metadata associated with a technique for generating a waveform, such as frequency, phase and amplitude parameters, is received. Data select signals and data input are generated based on the received metadata. In-phase and quadrature signals are produced at an output of a first de-multiplexer and a second de-multiplexer, respectively, based on the data select signals and the data input. Frequency modulated signals generated by direct digital synthesizers may be combined in a channel using a separate, distinct channel combiner.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.