Patents by Inventor Julia Zischang

Julia Zischang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12183696
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: December 31, 2024
    Assignee: Infineon Technologies AG
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Publication number: 20240113053
    Abstract: The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.
    Type: Application
    Filed: September 14, 2023
    Publication date: April 4, 2024
    Inventors: Andreas Korzenietz, Anton Mauder, Christoffer Erbert, Julia Zischang
  • Publication number: 20230395539
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Application
    Filed: August 18, 2023
    Publication date: December 7, 2023
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Patent number: 11764176
    Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang
  • Publication number: 20220059477
    Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 24, 2022
    Inventors: Evelyn Napetschnig, Jens Brandenburg, Christoffer Erbert, Joachim Hirschler, Oliver Humbel, Thomas Rupp, Carsten Schaeffer, Julia Zischang